wavelet_lifting_pld.tan.summary

小波提升Verilog代码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 8.200 ns
From           : s[23]
To             : odd_reg[23]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 23.200 ns
From           : y11[28]
To             : detail[28]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.300 ns
From           : s[1]
To             : odd_reg[1]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 45.45 MHz ( period = 22.000 ns )
From           : y11_per[0]
To             : y02[31]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : pre2_odd_reg[17]
To             : y11[18]
From Clock     : clk
To Clock       : clk
Failed Paths   : 244

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 244

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