booth_encoder.v

来自「为提高乘法运算速度本设计采用Booth算法」· Verilog 代码 · 共 87 行

// --------------------------------------------------------------------------------
//    
//              This confidential and proprietary software may be 
//            used only as authorized by a licensing agreement from 
//     Institute of Information and Communication Engineering,Zhejiang University.
//         In the event of publication, the following notice is applicable:
//    
//                    (C) COPYRIGHT 2000-2003 IICE@ZJU
//                           ALL RIGHTS RESERVED
//   
// ********************************************************************************
//
// Module         Booth_encoder
//
// FILE NAME    : Booth_encoder.v
//
// FUNCTION     : Booth_encoder Module 
//
// AUTHOR       : Zheng Wei   
//                
// VERSION      : Feb. 2003, V3.0
//
// ABSTRACT     :  Input ports     Description
//                 ===========     ===========
//                   code            3 bit
//
//		   ==============================================
//		   Output Ports:   Description
//    	           =============   ===========
//                    negative       
//                      one
//                      two
//                 ==============================================
//                 InOut Ports     Description
//                 ===========     ===========                 
// COPYRIGHT    :  2000-2003 (C) IICE@ZJU
// ********************************************************************************
//---------------------------------------------------------------------------------
//
//
module  Booth_encoder(//input potrs
                       code, Ae, 
                    //output ports
                    pp, negative
                    //inout ports
                   );
//                      
//------------------------input port declarations----------------------------------
//
input [2:0] code;
input [16:0] Ae;
//------------------------output port declarations---------------------------------
//
output [17:0] pp;
output negative;
//------------------------input signal declarations--------------------------------
//
wire [2:0] code;
wire [16:0] Ae;
//------------------------output signal declarations-------------------------------
//
reg [17:0] pp;
reg negative;
//-----------------------internal signal declarations------------------------------
//
//----------------------internal register declarations-----------------------------				
//
//---------------------------combinational logics----------------------------------
//
//---------------------------module instantiation----------------------------------
//
always @ (code or Ae)
case(code)
3'b000, 3'b111: begin pp = 18'b0; negative = 0; end
3'b001, 3'b010: begin pp = {Ae[16], Ae[16:0]}; negative = 0; end
3'b011:  begin pp = {Ae[16:0], 1'b0}; negative = 0; end
3'b100:  begin pp = {~Ae[16:0], 1'b1}; negative = 1; end
3'b101, 3'b110: begin
                negative = 1;
                pp = ~{Ae[16], Ae[16:0]};
                end
endcase                        
//----------------------------synchronous logics-----------------------------------
//
//
//
endmodulel