lcd1602.bld

Xilinx VerilogHDL_LCD驱动程序的源代码

Release 8.2.03i ngdbuild I.34
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

Command Line: C:\Xilinx\bin\nt\ngdbuild.exe -ise C:/Xilinx/spartan
3E/jupiter/LCD/LCD.ise -intstyle ise -dd _ngo -nt timestamp -uc LCD1602.ucf -p
xc3s500e-fg320-4 LCD1602.ngc LCD1602.ngd

Reading NGO file 'C:/Xilinx/spartan 3E/jupiter/LCD/LCD1602.ngc' ...

Applying constraints in "LCD1602.ucf" to the design...

Checking timing specifications ...
Checking Partitions ...
Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 69032 kilobytes

Writing NGD file "LCD1602.ngd" ...

Writing NGDBUILD log file "LCD1602.bld"...