hardware.c

应用于MC9S12DG128的ucos系统

/********************************************************************
                               //
//     Author: CaiXinBo      \\\\\\\                            //
//                          ( o   o )                           //
//----------------------oOO----(_)----OOo-----------------------//
                                                              
    FileName:       Hardware.c	
    Created Date:   23/5/2006   9:43
    Modify Date:    
    Purpose:	
*********************************************************************/
#include "includes.h"
#include "main.h"
#include "mc9s12dg128.h" 

/******************uart_init()****************/
void uart_init(void) {
SCI1CR2=0x0c;
SCI1BDH=0x00;
SCI1BDL=0x9C;
}

/**********uart_putchar()****************/
void uart_putchar(unsigned char ch)
{
while(!(SCI1SR1&0x80))
{}         
SCI1DRL=ch;
}


void ECT_Init(){
   TIOS=0X71;			      //PINS 7,1.2.3 input(pulse detector) and pins 0 4.5.6 as ouput(timer)
 												//0:input
 												//1:output
   TC0=18750;           //tc0 初值,18750*128/24/1000000=0.1s
   		
   TSCR2=0X07;				  //prescaler 1/128 bus clock sequence
      									//bit7:TOI timer overflow interrupt enable
      									//bits 2.1.0:timer prescaler select
      									//bit3:TCRE timer counter reset enable
      									
   TIE=0X01;	          //tco 开中断
   
   PACTL=0X52;          //pa使能,envent mode,rising edges ,overflow interrupt enable.
   											//bit 7     :no use
   											//bit 6 PAEN:PULSE ACCUMULATOR A system enable
   											//         0:16-bit accumulator a disable.
   											//         1:enable accumulator a system.
   											//bit 5 PAMOD: pulse accumulator mode 0:event counter mode
   											//                                    1:gated time accumulator mode
   											//bit 4:PEDGE: pulse accumulator edge cntrol 
   											//             0:falling edges on pt7 pin cause the count to be incremented.
   											//             1:rising edges on PT7 pin cause the count to be incremented.
                        //bit 3,2 CLK1,CLK0:CLOCK select bits
                        //                  00:use timer prescaler clock as timer ocunter clock
                        //                  01:use PACLK as input to timer counter clock
                        //                  10:use PACLK/256 as timer counter clock frequency
                        //                  11:use PACLK/65536 as timer counter clock frequency
                        //bit 1 PAOVI:pulse accumulator a overflow interrupt enable
                        //bit 0 PAI:pulse accumulator input interrupt enalbe
    MCCTL=0X47;		      //down_counter control,reload the latest value to count register,reture contents of load register
                        //bit7 MCZI:modulus counter underflow interrupt enable
                        //          0:disable
                        //          1:enable 
                        //bit6 MODMC:modulus mode enable 
                        //          0:the counter counts once from the value written to it and will stop at $0000
                        //					1:modulus mode is enabled.when the counter reaches $0000,the counter is loaded  
                        //            with the latest value written to the modulus count register
                        //bit5 RDMCL:read modulus DOwn-counter load
                        //           0:reads of the modulus count register will return the present value of the count register
                        //           1:reads of the modulus count register eill return the contents of the load register.
                        //bit4 ICLAT:when input capture latch mode is enabled(LATQ and BUFENbit in ICSYS($2B)are set, a write one
                        //           to this bi immediately forces the contents of the input capture registers TC0 to TC3 and their
                        //           corresponding 8-bit pulse accumulators to be latched into the associated holding registers.the 
                        //           pulse accumulator will be automatically cleared when the latch action occurs.
                        //           
                        //           writing zero to this bit has no effect ,read of this bit will return always zero )
                        //bit3 FLMC: force load register into the modulus counter counter count register
                        //           this bit active only when the modulus down counter is enabled(MCEN=1)
                        //           A write one to this bitloads the load register into the modulus counter count register.
                        //           this also resets the modulus counter prescaler
                        //           when MODMC=0 counter starts counting and stops at $0000
                        //bit2 MCEN: modulus down counter enable
                        //bit1,0 MCPR1,MCPR0:modulus counter prescaler select
                                             
  MCCNT=0Xea60;				  //down counter number, very 40ms read the hold register
        
  DLYCT=0X10;		        //delay for 256 bus clock about 10.4us
  
  ICOVW=0Xff;		        //enable overwrite
  TCTL4=0X55;		  
  ICSYS=0X03; 
  
  
  TSCR1=0X80;           //enable main timer
  }
  

/*HardwareInit(void)*/
void HardwareInit(void)
{
	uart_init();
	CLKSEL=0x00;            
  PLLCTL=0xe1;           
  SYNR=2;
  REFDV=1;         
  PLLCTL=0x60; 
  asm NOP;asm NOP;asm NOP;
 
  while(0==(CRGFLG&0x08));
  CLKSEL=0x80;             //pll start
 
  ECT_Init();
}