📄 fet140_sd16_grpchsingconv_lpm.c
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//******************************************************************************
// MSP-FET430P140 Demo - SD16, Enter LPM after Single Conversion on Group of
// Channels
//
// This example shows how to perform a single SD16 conversion on a group of
// channels and then enter Low Power mode. It uses internal reference and
// performs a single conversion on channels 0,1&2. The conversion results are
// stored in SD16MEM0,1 &2. Test by applying a voltage to channels, then
// setting and running to a break point at the mentioned instruction. To view
// the conversion results, open watch window in C-Spy and view the contents of
// "results".
//
// This example uses the Interrupt vector to determine the source of the
// Interrupt
// MSP430FE427
// ---------------
// | |
// | I1+ |<---- Vin 1+
// | I1- |<---- Vin 1-
// | I2+ |<---- Vin 2+
// | I2- |<---- Vin 2-
// | V1+ |<---- Vin 3+
// | V1- |<---- Vin 3-
// | |
//
//
// Harman Grewal
// Texas Instruments, Inc
// Oct, 2004
// IAR Embedded Workbench Version: 2.21B
//******************************************************************************
#include "msp430xE42x.h" // Standard Equations
static unsigned int results[3]; // Needs to be global in this example
// Otherwise, the compiler removes it
// because it is not used for anything.
void main(void)
{
volatile unsigned int i;
WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer
FLL_CTL0 |= XCAP14PF; // Set load capacitance for xtal.
for (i = 0; i < 20000; i++); // Delay - to allow watch crystal to stabilize.
P1DIR = 0xFF;
P1OUT = 0;
P2DIR = 0xFF;
P2OUT = 0;
SD16CTL = SD16REFON+SD16SSEL0; // Turn on SD16 Ref,SMCLK
SD16CCTL0 |= SD16SNGL+SD16GRP+SD16IE; // Enable Grouping with next higher channel,
// Single Conv
SD16CCTL1 |= SD16SNGL+SD16GRP+SD16IE; // Enable Grouping with next higher channel,
// Single Conv
SD16CCTL2 |= SD16SNGL+SD16IE; // Single Conv, Interrupt Enable
_EINT(); // Enable interrupts
for ( i=0; i<0x3600; i++); // Delay for reference start-up
while (1)
{
SD16CCTL2 |= SD16SC; // Start conversion
_BIS_SR(LPM0_bits); // Enter LPM0
}
}
enum
{
NO_INT = 0,
SDM0 = 4,
SDM1 = 6,
SDM2 = 8
};
#pragma vector=SD16_VECTOR
__interrupt void SD16ISR (void)
{
switch (SD16IV)
{
case NO_INT: break;
case SDM0: results[0] = SD16MEM0; break; // Move results, IFG is cleared
case SDM1: results[1] = SD16MEM1; break; // Move results, IFG is cleared
case SDM2: results[2] = SD16MEM2; SD16CTL= 0;LPM3;break;
// Move results, IFG is cleared
// LPM3 or 4
default: break;
}
}
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