📄 fet140_ta_pwm06.c
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//*******************************************************************************
// MSP-FET430P140 Demo - Timer_A PWM TA1-2 up-down mode, HF XTAL ACLK
//
// Description; This program will generate a two PWM outputs on P1.2/1.3 using
// Timer_A in an up-down mode. The value in CCR0, 128, defines the period/2 and the
// values in CCR1 and CCR2 the duty PWM cycles. Using HF XTAL ACLK as TACLK,
// the timer period is HF XTAL/256 with a 75% duty cycle on P1.2 and 25% on P1.3.
// ACLK = MCLK = TACLK = HF XTAL
// //** HF XTAL REQUIRED AND NOT INSTALLED ON FET **//
//
// MSP430F149
// -----------------
// /|\| XIN|-
// | | | HF XTAL (455k - 8Mhz)
// --|RST XOUT|-
// | |
// | P1.2|--> CCR1 - 75% PWM
// | P1.3|--> CCR2 - 25% PWM
//
// M.Buccini
// Texas Instruments, Inc
// August 2003
// Built with IAR Embedded Workbench Version: 1.26B
// January 2004
// Updated for IAR Embedded Workbench Version: 2.21B
//******************************************************************************
#include <msp430x14x.h>
void main(void)
{
unsigned int i;
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
BCSCTL1 |= XTS; // ACLK= LFXT1= HF XTAL
do
{
IFG1 &= ~OFIFG; // Clear OSCFault flag
for (i = 0xFF; i > 0; i--); // Time for flag to set
}
while ((IFG1 & OFIFG)); // OSCFault flag still set?
BCSCTL2 |= SELM_3; // MCLK= LFXT1 (safe)
P1DIR |= 0x0C; // P1.2 and P1.3 output
P1SEL |= 0x0C; // P1.2 and P1.3 TA1/2 otions
CCR0 = 128; // PWM Period/2
CCTL1 = OUTMOD_6; // CCR1 toggle/set
CCR1 = 32; // CCR1 PWM duty cycle
CCTL2 = OUTMOD_6; // CCR2 toggle/set
CCR2 = 96; // CCR2 PWM duty cycle
TACTL = TASSEL_1 + MC_3; // ACLK, up-down mode
_BIS_SR(CPUOFF); // Enter LPM0
}
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