📄 rtxconf.lst
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389 PUBLIC ?RTX_NM_IE2, ?RTX_D_IE2, ?RTX_ND_IE2
390
391 ; System Timer constants
392 PUBLIC ?RTX_CLK_INT_NBR ; EQUATE
393 PUBLIC ?RTX_TLOW, ?RTX_THIGH, ?RTX_TMOD ; DATA
394 PUBLIC ?RTX_TCON ; DATA
395 PUBLIC ?RTX_TFLAG, ?RTX_TCONTROL ; BIT
396 PUBLIC ?RTX_TMOD_AND_MASK, ?RTX_TMOD_OR_MASK ; EQUATES
397 PUBLIC ?RTX_TCON_AND_MASK, ?RTX_TCON_OR_MASK ; EQUATES
398
399 ; Bank-Switching Support
400 PUBLIC ?RTX_SWITCHBANK ; CODE
401 PUBLIC ?RTX_SAVE_INT_BANK ; DATA
402 IF (?RTX_BANKSWITCHING = 0)
403 PUBLIC ?B_CURRENTBANK ; Dummy DATA-Definition
404 ENDIF
405
406 ; Idle function
407 PUBLIC ?RTX_IDLE_FUNC
408
409 ; Mailbox and semaphore FIFO space
410 PUBLIC ?RTX_MBX_PAGE
411 PUBLIC ?RTX_MBX_PAGE_END
412 PUBLIC ?RTX_SEM_PAGE
413 PUBLIC ?RTX_SEM_PAGE_END
414
415
416 ;*----------------------------------------------------------------------*
417 ;* MACROS
418 ;*----------------------------------------------------------------------*
419
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 03/21/2008 10:42:14 PAGE 7
420 ; This MACRO generates an RTX-51 interrupt entry point using the base
421 ; address ?RTX_INTBASE.
422
423 INT_ENTRY MACRO NO
424 EXTRN XDATA (?RTX_INT&NO&_TID)
425 PUBLIC INT&NO&_VECTOR
426 CSEG AT(?RTX_INTBASE+3+(&NO&*8))
427 INT&NO&_VECTOR: MOV ?RTX_TMP1, A ; Save A
428 MOV A, #LOW(?RTX_INT&NO&_TID); Set up ptr to int. TID
429 LJMP ?RTX_INT_HANDLER ; Jump to general ISR
430 ENDM
431
432
433 ;*----------------------------------------------------------------------*
434 ;* PROCESSOR SPECIFIC DATA DEFINITIONS
435 ;*----------------------------------------------------------------------*
436
ELSEIF (?RTX_CPU_TYPE = 21)
801 ;**********
802 ;* Type 21 *
803 ;**********
804 ;------------------------------------------------------------------
805 ; Define the number and addresses of the interrupt enable registers
806 ; C515C -> 3 interrupt enable registers
807 ; (Set the not used registers to the same address as ?RTX_IE)
808
0003 809 INT_EN_MASK_NUMBER EQU 3
00A8 810 ?RTX_IE DATA 0A8H
00E6 811 ?RTX_IEN1 DATA 0E6H
00E7 812 ?RTX_IEN2 DATA 0E7H
813
814 ;------------------------------------------------------------------
815 ; Generate the interrupt entry points supported by the peripherals
816 ; of the selected CPU type.
817 IF (?RTX_SYSTEM_TIMER = 0)
818 ; Do NOT include the Timer 0 Vector (INT-1)
826 ;
INT_1 (Timer 0)
855 ;
INT_6 not used(WDT)
856 ;
INT_7 not used(EAL)
899 ;
INT_14 not used(SWDT)
900 ;
INT_15 not used(EXEN2)
901 ; INT_16
not used
ENDIF
990
991 ;------------------------------------------------------------------
992 ; The following table attaches the interrupt numbers (0..31) to the
993 ; corresponding bits in the interrupt enable masks of the specific
994 ; processor.
995 ; All three interrupt enable register contents must be defined
996 ; for every interrupt number (even when the specific processor contains
997 ; only one interrupt mask).
998 ; Syntax: DB IE-content, IE1-content, IE2-content
999 ;
1000 ?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF SEGMENT CODE
---- 1001 RSEG ?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF
1002
0000 1003 ?RTX_INT_TO_BIT_TABLE_BASE:
0000 010000 1004 DB 01H, 00H, 00H ; INT_0 (P3.2/INT0)
0003 020000 1005 DB 02H, 00H, 00H ; INT_1 (Timer 0)
0006 040000 1006 DB 04H, 00H, 00H ; INT_2 (P3.3/INT1)
0009 080000 1007 DB 08H, 00H, 00H ; INT_3 (Timer 1)
000C 100000 1008 DB 10H, 00H, 00H ; INT_4 (Ser. channel 0)
000F 200000 1009 DB 20H, 00H, 00H ; INT_5 (Timer 2/ ext. reload)
0012 000000 1010 DB 00H, 00H, 00H ; INT_6 not used(WDT)
0015 000000 1011 DB 00H, 00H, 00H ; INT_7 not used(EAL)
1012
0018 000100 1013 DB 00H, 01H, 00H ; INT_8 (A/D-Converter)
001B 000200 1014 DB 00H, 02H, 00H ; INT_9 (P1.4/INT2/CC4)
001E 000400 1015 DB 00H, 04H, 00H ; INT_10 (P1.0/INT3/CC0)
0021 000800 1016 DB 00H, 08H, 00H ; INT_11 (P1.1/INT4/CC1)
0024 001000 1017 DB 00H, 10H, 00H ; INT_12 (P1.2/INT5/CC2)
0027 002000 1018 DB 00H, 20H, 00H ; INT_13 (P1.3/INT6/CC3)
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 03/21/2008 10:42:14 PAGE 8
002A 000000 1019 DB 00H, 00H, 00H ; INT_14 not used(SWDT)
002D 000000 1020 DB 00H, 00H, 00H ; INT_15 not used(EXEN2)
1021
0030 000000 1022 DB 00H, 00H, 00H ; INT_16 not used
0033 000002 1023 DB 00H, 00H, 02H ; INT_17 CAN Controller
0036 000004 1024 DB 00H, 00H, 04H ; INT_18 SSC
0039 000000 1025 DB 00H, 00H, 00H ; INT_19 not used
003C 000010 1026 DB 00H, 00H, 10H ; INT_20 (P7.0/INT7)
003F 000020 1027 DB 00H, 00H, 20H ; INT_21 (P4.5/INT8)
1028
1029 ;------------------------------------------------------------------
1030 ; Define the greatest supported interrupt number
0015 1031 ?RTX_MAX_INT_NBR EQU 21
1032
0087 1033 PCON DATA 87H
1034
1035 ENTER_IDLE MACRO
1036 ;;
1037 ;; Enter Idle Mode
1038 ;; ---------------
1039 ;; To be used whenever entering idle state.
1040 ;;
1041 ORL PCON, #01H ; Set idle mode (leave by interrupt)
1042 ORL PCON, #20H ; (peripherals stay active)
1043 ENDM
1044
1045
1046
$endif
2425
2426
2427
2428 $eject
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 03/21/2008 10:42:14 PAGE 9
2429 ;*----------------------------------------------------------------------*
2430 ;* DEFINITIONS COMMON FOR ALL PROCESSORS
2431 ;*----------------------------------------------------------------------*
2432
2433 ;------------------------------------------------------------------
2434 ; Define the internal interrupt mask variables. The variables are
2435 ; used for the Interrupt-Handling.
2436 ; Initialise the enable bits for the Interrupt-Enable-Masks
2437 ;
ELSEIF (INT_EN_MASK_NUMBER = 3)
2485 ?RTX?INT_MASK?RTXCONF SEGMENT DATA
---- 2486 RSEG ?RTX?INT_MASK?RTXCONF
2487 ; variables for first mask
0000 2488 ?RTX_NM_IE: DS 1
0001 2489 ?RTX_D_IE: DS 1
0002 2490 ?RTX_ND_IE: DS 1
2491 ; variables for second mask
0003 2492 ?RTX_NM_IE1: DS 1
0004 2493 ?RTX_D_IE1: DS 1
0005 2494 ?RTX_ND_IE1: DS 1
2495 ; variables for third mask
0006 2496 ?RTX_NM_IE2: DS 1
0007 2497 ?RTX_D_IE2: DS 1
0008 2498 ?RTX_ND_IE2: DS 1
2499
2500 ; RTX-51 calls this routine in the initialisation phase
2501 ?RTX?RTX_INIT_INT_REG_FLAGS?RTXCONF SEGMENT CODE
---- 2502 RSEG ?RTX?RTX_INIT_INT_REG_FLAGS?RTXCONF
0000 2503 ?RTX_INIT_INT_REG_FLAGS:
0000 D200 F 2504 SETB ?RTX_ENA_INT_REG1
0002 D200 F 2505 SETB ?RTX_ENA_INT_REG2
0004 22 2506 RET
2507 ENDIF
2508
2509
2510 ;------------------------------------------------------------------
2511 ; Define the System-Timer specific values
2512 ; This values are normally for all 8051 family-members identical.
2513 ;
2514 IF (?RTX_SYSTEM_TIMER = 0)
008A 2515 ?RTX_TLOW DATA 8AH
008C 2516 ?RTX_THIGH DATA 8CH
0088 2517 ?RTX_TCON DATA 88H
0089 2518 ?RTX_TMOD DATA 89H
008D 2519 ?RTX_TFLAG BIT 8DH
008C 2520 ?RTX_TCONTROL BIT 8CH
2521 ; TCON init-masks
2522 ; The clock will be initialized with: ANL TCON, #RTX_TCON_AND_MASK
2523 ; ORL TCON, #RTX_TCON_OR_MASK
2524 ; --> not used for this timer
00FF 2525 ?RTX_TCON_AND_MASK EQU 0FFH
0000 2526 ?RTX_TCON_OR_MASK EQU 000H
2527 ; TMOD init-masks
2528 ; The clock will be initialized with: ANL TMOD, #RTX_TMOD_AND_MASK
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