📄 rtxconf.lst
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+1 190 ; ===========================================
+1 191 ;
+1 192 ; Some 8051 family members have specific bits in their Interrupt-Enable
+1 193 ; Registers, which have other functions than interrupt enable/disable.
+1 194 ; Here you can set the initial values of these special bits.
+1 195 ; (Normally RTX-51 will set all not used bits in the interrupt enable mask
+1 196 ; to 0).
+1 197 ; You MUST NOT set bits dedicated to interrupt enable/disable !
+1 198 ; NOTE: ?RTX_IEN1_INIT is only used for processors with at least 2 interrupt
+1 199 ; masks.
+1 200 ; ?RTX_IEN2_INIT is only used for processors with 3 interrupt masks.
+1 201 ;
0000 +1 202 ?RTX_IE_INIT EQU 0
0000 +1 203 ?RTX_IEN1_INIT EQU 0
0000 +1 204 ?RTX_IEN2_INIT EQU 0
+1 205
+1 206
+1 207 ; 4. FAST TASK STACK- AND ENVIRONMENT SIZE
+1 208 ; ========================================
+1 209 ;
+1 210 ; This constant defines the stack- and environment size reserved per
+1 211 ; defined fast task. These areas are located in IDATA space.
+1 212 ;
+1 213 ; Minimum values (per task):
+1 214 ; - 3 Bytes for internal use
+1 215 ; - 2 Bytes for the task code start address
+1 216 ; Do not set to less than 9 bytes
+1 217 ; Add 3 Bytes when code bank switching is used (?RTX_BANKSWITCHING = 1) !
+1 218 ; (Default value: 12 Bytes)
+1 219 ;
0018 +1 220 ?RTX_INTSTKSIZE EQU 24
+1 221
+1 222
+1 223 ; 5. STANDARD TASK CONTEXT STACK SIZE
+1 224 ; ===================================
+1 225 ;
+1 226 ; This constant defines the maximum size of stack data stored in the
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 03/21/2008 10:42:14 PAGE 4
+1 227 ; context area of a standard task. For each defined standard task such an
+1 228 ; area is reserved in XDATA space.
+1 229 ;
+1 230 ; (Default value: 32 Bytes)
+1 231 ;
0020 +1 232 ?RTX_EXTSTKSIZE EQU 32
+1 233
+1 234
+1 235 ; 6. REENTRANT STACK SIZE
+1 236 ; =======================
+1 237 ;
+1 238 ; This constnat defines the maximum size of the reentrant stack. For each
+1 239 ; defined task such an area is reserved in XDATA space.
+1 240 ;
+1 241 ; The greatest possible reentrant-stack size is 256-18-?RTX_EXTSTKSIZE !!
+1 242 ; (Default value: 50 Bytes)
+1 243 ;
0032 +1 244 ?RTX_EXTRENTSIZE EQU 50
+1 245
+1 246
+1 247 ; 7. ROUND ROBIN FLAG
+1 248 ; ===================
+1 249 ;
+1 250 ; 0 --> Do not use round robin scheduling
+1 251 ; 1 --> Use round robin scheduling
+1 252 ; (Default value: 0)
+1 253 ;
0000 +1 254 ?RTX_TIMESHARING EQU 0
+1 255
+1 256
+1 257 ; 8. BANK SWITCHING FLAG
+1 258 ; ======================
+1 259 ;
+1 260 ; For code bank switching details see BL51 documentation and READ.ME file
+1 261 ; 0 --> code bank switching is disabled
+1 262 ; 1 --> code bank switching is enabled
+1 263 ; (Default value: 0)
+1 264 ;
+1 265 ; !!! IMPORTANT NOTICE !!!
+1 266 ; Set ?B_RTX contained in L51_BANK.A51 (V1.4b up) to one, when using
+1 267 ; code bank switching together with RTX-51
+1 268 ;
0000 +1 269 ?RTX_BANKSWITCHING EQU 0
+1 270
+1 271
+1 272 ; 9. INTERRUPT TABLE BASE ADDRESS
+1 273 ; ===============================
+1 274 ;
+1 275 ; Normally the interrupt table is located at address 0000H. For special
+1 276 ; hardware configurations, like flash eprom systems, there may be a need
+1 277 ; to reroute interrupts to a table at a different address. If an address
+1 278 ; different than 0000H is used, then the user has to supply code to re-
+1 279 ; route each used interrupt vector to an address with the offset declared
+1 280 ; below.
+1 281 ; For standard systems this address has to be 0000H.
+1 282 ;
0000 +1 283 ?RTX_INTBASE EQU 0
+1 284
+1 285
+1 286 ; 10. MAILBOX-SUPPORT FLAG
+1 287 ; ========================
+1 288 ;
+1 289 ; This flag determines if memory is allocated for the mailbox FIFOs or not.
+1 290 ; If set to 0, then no wait for a mailbox is possible. Associated calls
+1 291 ; will return a NOT_OK in this case.
+1 292 ; Set ?RTX_MAILBOX_SUPPORT to 0 if mailbox services are not desired.
+1 293 ; Set ?RTX_MAILBOX_SUPPORT to 1 if mailbox services are desired.
+1 294 ; (Default is 1)
+1 295 ;
0001 +1 296 ?RTX_MAILBOX_SUPPORT EQU 1
+1 297
+1 298
+1 299 ; 11. SEMAPHORE-SUPPORT FLAG
+1 300 ; ==========================
+1 301 ;
+1 302 ; This flag determines if memory is allocated for the semaphore FIFOs or not.
+1 303 ; If set to 0, then no wait for a semaphore is possible. Associated calls
+1 304 ; will return a NOT_OK in this case.
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 03/21/2008 10:42:14 PAGE 5
+1 305 ; Set ?RTX_SEMAPHORE_SUPPORT to 0 if semaphore services are not desired.
+1 306 ; Set ?RTX_SEMAPHORE_SUPPORT to 1 if semaphore services are desired.
+1 307 ; (Default is 1)
+1 308 ; NOTE: if an increased XDATA usage compared with RTX-51 V 4.x has to be
+1 309 ; avoided, then this flag should be set to 0 !
+1 310 ;
0001 +1 311 ?RTX_SEMAPHORE_SUPPORT EQU 1
+1 312
+1 313
+1 314 ; 12. IDLE MODE
+1 315 ; =============
+1 316 ;
+1 317 ; If this option is enabled, then each time the RTX idle loop is
+1 318 ; entered the cpu is switched to idle mode. This feature is supported
+1 319 ; for selected cpu's only. enabling it for other cpu's will have no effect.
+1 320 ;
+1 321 ; USE_IDLE = 0: do not use the idle mode
+1 322 ; = 1: set cpu to idle mode during system idle time
+1 323
0000 +1 324 ?RTX_USE_IDLE EQU 0
+1 325
+1 326
+1 327 ;*----------------------------------------------------------------------*
+1 328 ;* END of INCLUDE FILE RTXSETUP.DCL *
+1 329
330
331
332 ;========================================================================
333 ; END OF USER-CONFIGURABLE SECTION
334 ;========================================================================
335
336
337 $eject
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 03/21/2008 10:42:14 PAGE 6
338 ;************************************************************************
339 ;* *
340 ;* THE FOLLOWING SECTIONS MUST NORMALLY NOT BE ALTERED BY THE USER *
341 ;* --------------------------------------------------------------- *
342 ;* *
343 ;************************************************************************
344
345 NAME ?RTX?CONFIGURATION ; Do NOT alter the modulename !
346
347 ;*----------------------------------------------------------------------*
348 ;* IMPORTS
349 ;*----------------------------------------------------------------------*
350
351 EXTRN BIT (?RTX_ENA_INT_REG1, ?RTX_ENA_INT_REG2) ; from RTXDATA
352 EXTRN CODE (?RTX_SYSCLK_INTHNDLR) ; from RTXCLK
353 EXTRN CODE (?RTX_INT_HANDLER) ; from RTXINT
354 EXTRN DATA (?RTX_TMP1) ; from RTXDATA
355
ENDIF
361
362 ;*----------------------------------------------------------------------*
363 ;* EXPORTS
364 ;*----------------------------------------------------------------------*
365
366 ; System constants
367 PUBLIC ?RTX_EXTRENTSIZE, ?RTX_EXTSTKSIZE, ?RTX_INTSTKSIZE
368 PUBLIC ?RTX_TIMESHARING, ?RTX_BANKSWITCHING, ?RTX_INTREGSIZE
369 PUBLIC ?RTX_MAILBOX_SUPPORT, ?RTX_SEMAPHORE_SUPPORT
370
371 ; Initial Interrupt mask values
372 PUBLIC ?RTX_IE_INIT, ?RTX_IEN1_INIT, ?RTX_IEN2_INIT
373
374 ; Enable the interrupt enable registers for the selected processor
375 PUBLIC ?RTX_INIT_INT_REG_FLAGS
376
377 ; Interrupt number to enable-mask table
378 PUBLIC ?RTX_INT_TO_BIT_TABLE_BASE
379
380 ; Greatest interrupt number
381 PUBLIC ?RTX_MAX_INT_NBR
382
383 ; Processor specific interrupt enable masks
384 PUBLIC ?RTX_IE, ?RTX_IEN1, ?RTX_IEN2
385
386 ; Interrupt mask variables
387 PUBLIC ?RTX_NM_IE, ?RTX_D_IE, ?RTX_ND_IE
388 PUBLIC ?RTX_NM_IE1, ?RTX_D_IE1, ?RTX_ND_IE1
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