📄 s3c2410.h
字号:
#define MRSR_WBL_Burst FInsrt(0x0, fBANKCON_WBL) /* Burst(Fixed) */#define fMRSR_TM Fld(2,7) /* Test Mode */#define MRSR_TM FMsk(fMRSR_TM)#define MRSR_TM_Set FInsrt(0x0, fBANKCON_TM) /* Mode Register set(Fixed) */#define fMRSR_CL Fld(3,4) /* CAS Latency */#define MRSR_CL FMsk(fMRSR_CL)#define MRSR_CL1 FInsrt(0x0, fBANKCON_CL) /* 1 clock */#define MRSR_CL2 FInsrt(0x2, fBANKCON_CL) /* 2 clocks */#define MRSR_CL3 FInsrt(0x3, fBANKCON_CL) /* 3 clocks */#define fMRSR_BT Fld(1,3) /* Burst Type */#define MRSR_BT FMsk(fMRSR_BT)#define MRSR_BT_Seq FInsrt(0x0, fBANKCON_BT) /* sequential(Fixed) */#define fMRSR_BL Fld(3,0) /* Burst Length */#define MRSR_BL FMsk(fMRSR_BL)#define MRSR_BL1 FInsrt(0x0, fBANKCON_BL) /* 1 (Fixed) *//* Clock and Power Management */#define CLK_CTL_BASE 0x4C000000#define bCLKCTL(Nb) __REG(CLK_CTL_BASE + (Nb))/* Offset */#define oLOCKTIME 0x00 /* R/W, PLL lock time count register */#define oMPLLCON 0x04 /* R/W, MPLL configuration register */#define oUPLLCON 0x08 /* R/W, UPLL configuration register */#define oCLKCON 0x0C /* R/W, Clock generator control reg. */#define oCLKSLOW 0x10 /* R/W, Slow clock control register */#define oCLKDIVN 0x14 /* R/W, Clock divider control *//* Registers */#define LOCKTIME bCLKCTL(oLOCKTIME)#define MPLLCON bCLKCTL(oMPLLCON)#define UPLLCON bCLKCTL(oUPLLCON)#define CLKCON bCLKCTL(oCLKCON)#define CLKSLOW bCLKCTL(oCLKSLOW)#define CLKDIVN bCLKCTL(oCLKDIVN)/* Fields */#define fPLL_MDIV Fld(8,12)#define fPLL_PDIV Fld(6,4)#define fPLL_SDIV Fld(2,0)/* bits */#define CLKCON_SPI (1<<18)#define CLKCON_IIS (1<<17)#define CLKCON_IIC (1<<16)#define CLKCON_ADC (1<<15)#define CLKCON_RTC (1<<14)#define CLKCON_GPIO (1<<13)#define CLKCON_UART2 (1<<12)#define CLKCON_UART1 (1<<11)#define CLKCON_UART0 (1<<10)#define CLKCON_SDI (1<<9)#define CLKCON_PWM (1<<8)#define CLKCON_USBD (1<<7)#define CLKCON_USBH (1<<6)#define CLKCON_LCDC (1<<5)#define CLKCON_NAND (1<<4)#define CLKCON_POWEROFF (1<<3)#define CLKCON_IDLE (1<<2)/* * I/O Port (Page 9-8) * * Register GPACON Port A Control [word, R/W, 0x7ffff] GPADAT Port A Data [word, R/W, ?] GPBCON Port B Control [word, R/W, 0x0] GPBDAT Port B Data [word, R/W, ?] GPBUP Pull-up Control B (low active) [word, R/W, 0x0] GPCCON Port C Control [word, R/W, 0x0] GPCDAT Port C Data [word, R/W, ?] GPCUP Pull-up Control C (low active) [word, R/W, 0x0] GPDCON Port D Control [word, R/W, 0x0] GPDDAT Port D Data [word, R/W, ?] GPDUP Pull-up Control D (low active) [word, R/W, 0xF000] GPECON Port E Control [word, R/W, 0x0] GPEDAT Port E Data [word, R/W, ?] GPEUP Pull-up Control E (low active) [word, R/W, 0x0] GPFCON Port F Control [word, R/W, 0x0] GPFDAT Port F Data [word, R/W, ?] GPFUP Pull-up Control F (low active) [word, R/W, 0x0] GPGCON Port G Control [word, R/W, 0x0] GPGDAT Port G Data [word, R/W, ?] GPGUP Pull-up Control G (low active) [word, R/W, 0xF800] GPHCON Port H Control [word, R/W, 0x0] GPHDAT Port H Data [word, R/W, ?] GPHUP Pull-up Control H (low active) [word, R/W, 0x0] MISCCR Miscellaneous Control [word, R/W, 0x10330] DCLKCON DCLK0/1 Control [word, R/W, 0x0] EXTINT0 External Interrupt 0 Control [word, R/W, 0x0] EXTINT1 External Interrupt 0 Control [word, R/W, 0x0] EXTINT2 External Interrupt 0 Control [word, R/W, 0x0] EINFLT0 Reserved EINFLT1 Reserved EINFLT2 External Interrupt 2 Filter [word, R/W, 0x0] EINFLT3 External Interrupt 3 Filter [word, R/W, 0x0] EINTMASK External Interrupt Mask [word, R/W, 0x00fffff0] EINTPEND External Interrupt Pending [word, R/W, 0x0] GSTATUS0 General Status (External Pin status) [word, R, ?] GSTATUS1 General Status (Chip ID) [word, R/W, 0x32410000] * */#define GPIO_CTL_BASE 0x56000000#define bGPIO(p) __REG(GPIO_CTL_BASE + (p))#define MISCCR bGPIO(0x80)#define DCLKCON bGPIO(0x84)#define EXTINT0 bGPIO(0x88)#define EXTINT1 bGPIO(0x8c)#define EXTINT2 bGPIO(0x90)#define EINTFLT0 bGPIO(0x94)#define EINTFLT1 bGPIO(0x98)#define EINTFLT2 bGPIO(0x9c)#define EINTFLT3 bGPIO(0xa0)#define EINTMASK bGPIO(0xa4)#define EINTPEND bGPIO(0xa8)#define GSTATUS0 bGPIO(0xac)#define GSTATUS1 bGPIO(0xb0)#define GSTATUS2 bGPIO(0xb4)#define GSTATUS3 bGPIO(0xb8)#define GSTATUS4 bGPIO(0xbc)#define GPACON bGPIO(0x00)#define GPADAT bGPIO(0x04)#define GPBCON bGPIO(0x10)#define GPBDAT bGPIO(0x14)#define GPBUP bGPIO(0x18)#define GPCCON bGPIO(0x20)#define GPCDAT bGPIO(0x24)#define GPCUP bGPIO(0x28)#define GPDCON bGPIO(0x30)#define GPDDAT bGPIO(0x34)#define GPDUP bGPIO(0x38)#define GPECON bGPIO(0x40)#define GPEDAT bGPIO(0x44)#define GPEUP bGPIO(0x48)#define GPFCON bGPIO(0x50)#define GPFDAT bGPIO(0x54)#define GPFUP bGPIO(0x58)#define GPGCON bGPIO(0x60)#define GPGDAT bGPIO(0x64)#define GPGUP bGPIO(0x68)#define GPHCON bGPIO(0x70)#define GPHDAT bGPIO(0x74)#define GPHUP bGPIO(0x78)/* Miscellaneous */#define MISCCR_nRSTCON (1 << 16) /* nRSTOUT software control */#define MISCCR_USB0_SUSPEND (1 << 12) /* set USB port 0 to Sleep */#define MISCCR_USB1_SUSPEND (1 << 13) /* set USB port 1 to Sleep */#define fMISCCR_CLKSEL(x) Fld(3, 4*((x)+1))#define MISCCR_CLKSEL(x) FMsk(fMISCCR_CLKSEL(x)) /* select ? CLK with CLKOUTx pad */#define MISCCR_CLKSEL_MPLL(x) FInsrt(0x0, fMISCCR_CLKSEL(x))#define MISCCR_CLKSEL_UPLL(x) FInsrt(0x1, fMISCCR_CLKSEL(x))#define MISCCR_CLKSEL_FCLK(x) FInsrt(0x2, fMISCCR_CLKSEL(x))#define MISCCR_CLKSEL_HCLK(x) FInsrt(0x3, fMISCCR_CLKSEL(x))#define MISCCR_CLKSEL_PCLK(x) FInsrt(0x4, fMISCCR_CLKSEL(x))#define MISCCR_CLKSEL_DCLK(x) FInsrt(0x5, fMISCCR_CLKSEL(x))#define MISCCR_USBPAD (1 << 3) /* use pads related USB for 0: USB slave, 1: USB host */#define MISCCR_HZSTOP (1 << 2) /* 0: HZ@stop 1: previous state of PAD */#define MISCCR_SPUCR1 (1 << 1) /* DATA[31:16] port pull-up */#define MISCCR_SPUCR0 (1 << 0) /* DATA[15:0] port pull-up *//* DCLK control register */#define fDCLKCMP(x) Fld(4,8+16*(x)) /* DCLK Compare value clock */#define mDCLKCMP(x) FMsk(fDCLKCMP(x))#define DCLKCMP(x, y) Finsrt((y), fDCLKCMP(x))#define fDCLKDIV(x) Fld(4,4+16*(x)) /* DCLK divide value */#define mDCLKDIV(x) FMsk(fDCLKDIV(x))#define DCLKDIV(x, y) Finsrt((y), fDCLKDIV(x))#define DCLKSEL_PCLK(x) (0 << (1+16*(x)) /* Select PCLK as DCLK Source Clock */#define DCLKSEL_USB(x) (1 << (1+16*(x)) /* Select USBCLK as DCLK Source Clock */#define DCLK1CMP mDCLKCMP(1)#define DCLK1DIV mDCLKDIV(1)#define DCLK1SEL_PCLK DCLKSEL_PCLK(1)#define DCLK1SEL_USB DCLKSEL_USB(1)#define DCLK0CMP mDCLKCMP(0)#define DCLK0DIV mDCLKDIV(0)#define DCLK0SEL_PCLK DCLKSEL_PCLK(0)#define DCLK0SEL_USB DCLKSEL_USB(0)/* General Status */#define GSTAT0_nWAIT (1 << 3) /* Status of nWAIT pin */#define GSTAT0_NCON1 (1 << 2) /* Status of NCON1 pin */#define GSTAT0_NCON0 (1 << 1) /* Status of NCON0 pin */#define GSTAT0_BATT_FLT (1 << 0) /* Status of BATT_FLT pin *//* * 2002-10-08: Janghoon Lyu <nandy@mizi.com> * 货酚霸 矫档秦 壕聪促. * | MODE | PULLUP | PORT | OFFSET | */#define GPCON(x) __REG(0x56000000, (x) * 0x10)#define GPDAT(x) __REG(0x56000004, (x) * 0x10)#define GPUP(x) __REG(0x56000008, (x) * 0x10)#define GPIO_OFS_SHIFT 0#define GPIO_PORT_SHIFTT 8#define GPIO_PULLUP_SHIFT 16 #define GPIO_MODE_SHIFT 24#define GPIO_OFS_MASK 0x000000ff#define GPIO_PORT_MASK 0x0000ff00#define GPIO_PULLUP_MASK 0x00ff0000#define GPIO_MODE_MASK 0xff000000#define GPIO_MODE_IN (0 << GPIO_MODE_SHIFT)#define GPIO_MODE_OUT (1 << GPIO_MODE_SHIFT)#define GPIO_MODE_ALT0 (2 << GPIO_MODE_SHIFT)#define GPIO_MODE_ALT1 (3 << GPIO_MODE_SHIFT)#define GPIO_PULLUP_EN (0 << GPIO_PULLUP_SHIFT)#define GPIO_PULLUP_DIS (1 << GPIO_PULLUP_SHIFT) #define PORTA_OFS 0#define PORTB_OFS 1#define PORTC_OFS 2#define PORTD_OFS 3#define PORTE_OFS 4#define PORTF_OFS 5#define PORTG_OFS 6#define PORTH_OFS 7#define MAKE_GPIO_NUM(p, o) ((p << GPIO_PORT_SHIFTT) | (o << GPIO_OFS_SHIFT))#define GRAB_MODE(x) (((x) & GPIO_MODE_MASK) >> GPIO_MODE_SHIFT)#define GRAB_PULLUP(x) (((x) & GPIO_PULLUP_MASK) >> GPIO_PULLUP_SHIFT)#define GRAB_PORT(x) (((x) & GPIO_PORT_MASK) >> GPIO_PORT_SHIFTT)#define GRAB_OFS(x) (((x) & GPIO_OFS_MASK) >> GPIO_OFS_SHIFT)#define set_gpio_ctrl(x) \ ({ GPCON(GRAB_PORT((x))) &= ~(0x3 << (GRAB_OFS((x))*2)); \ GPCON(GRAB_PORT(x)) |= (GRAB_MODE(x) << (GRAB_OFS((x))*2)); \ GPUP(GRAB_PORT((x))) &= ~(1 << GRAB_OFS((x))); \ GPUP(GRAB_PORT((x))) |= (GRAB_PULLUP((x)) << GRAB_OFS((x))); })#define set_gpio_pullup(x) \ ({ GPUP(GRAB_PORT((x))) &= ~(1 << GRAB_OFS((x))); \ GPUP(GRAB_PORT((x))) |= (GRAB_PULLUP((x)) << GRAB_OFS((x))); })#define set_gpio_pullup_user(x, v) \ ({ GPUP(GRAB_PORT((x))) &= ~(1 << GRAB_OFS((x))); \ GPUP(GRAB_PORT((x))) |= ((v) << GRAB_OFS((x))); })#define set_gpio_mode(x) \ ({ GPCON(GRAB_PORT((x))) &= ~(0x3 << (GRAB_OFS((x))*2)); \ GPCON(GRAB_PORT((x))) |= (GRAB_MODE((x)) << (GRAB_OFS((x))*2)); })#define set_gpio_mode_user(x, v) \ ({ GPCON(GRAB_PORT((x))) & = ~(0x3 << (GRAB_OFS((x))*2)); \ GPCON(GRAB_PORT((x))) |= ((v) << (GRAB_OFS((x))*2)); })#define set_gpioA_mode(x) \ ({ GPCON(GRAB_PORT((x))) &= ~(0x1 << GRAB_OFS((x))); \ GPCON(GRAB_PORT((x))) |= (GRAB_MODE((x)) << GRAB_OFS((x))); })#define read_gpio_bit(x) ((GPDAT(GRAB_PORT((x))) & (1<<GRAB_OFS((x)))) >> GRAB_OFS((x)))#define read_gpio_reg(x) (GPDAT(GRAB_PORT((x)))#define write_gpio_bit(x, v) \ ({ GPDAT(GRAB_PORT((x))) &= ~(0x1 << GRAB_OFS((x))); \ GPDAT(GRAB_PORT((x))) |= ((v) << GRAB_OFS((x))); })#define write_gpio_reg(x, v) (GPDAT(GRAB_PORT((x))) = (v)) #define GPIO_A0 MAKE_GPIO_NUM(PORTA_OFS, 0)#define GPIO_A1 MAKE_GPIO_NUM(PORTA_OFS, 1)#define GPIO_A2 MAKE_GPIO_NUM(PORTA_OFS, 2)#define GPIO_A3 MAKE_GPIO_NUM(PORTA_OFS, 3)#define GPIO_A4 MAKE_GPIO_NUM(PORTA_OFS, 4)#define GPIO_A5 MAKE_GPIO_NUM(PORTA_OFS, 5)#define GPIO_A6 MAKE_GPIO_NUM(PORTA_OFS, 6)#define GPIO_A7 MAKE_GPIO_NUM(PORTA_OFS, 7)#define GPIO_A8 MAKE_GPIO_NUM(PORTA_OFS, 8)#define GPIO_A9 MAKE_GPIO_NUM(PORTA_OFS, 9)#define GPIO_A10 MAKE_GPIO_NUM(PORTA_OFS, 10)#define GPIO_A11 MAKE_GPIO_NUM(PORTA_OFS, 11)#define GPIO_A12 MAKE_GPIO_NUM(PORTA_OFS, 12)#define GPIO_A13 MAKE_GPIO_NUM(PORTA_OFS, 13)#define GPIO_A14 MAKE_GPIO_NUM(PORTA_OFS, 14)#define GPIO_A15 MAKE_GPIO_NUM(PORTA_OFS, 15)#define GPIO_A16 MAKE_GPIO_NUM(PORTA_OFS, 16)#define GPIO_A17 MAKE_GPIO_NUM(PORTA_OFS, 17)#define GPIO_A18 MAKE_GPIO_NUM(PORTA_OFS, 18)#define GPIO_A19 MAKE_GPIO_NUM(PORTA_OFS, 19)#define GPIO_A20 MAKE_GPIO_NUM(PORTA_OFS, 20)#define GPIO_A21 MAKE_GPIO_NUM(PORTA_OFS, 21)#define GPIO_A22 MAKE_GPIO_NUM(PORTA_OFS, 22)#define GPIO_B0 MAKE_GPIO_NUM(PORTB_OFS, 0)#define GPIO_B1 MAKE_GPIO_NUM(PORTB_OFS, 1)#define GPIO_B2 MAKE_GPIO_NUM(PORTB_OFS, 2)#define GPIO_B3 MAKE_GPIO_NUM(PORTB_OFS, 3)#define GPIO_B4 MAKE_GPIO_NUM(PORTB_OFS, 4)#define GPIO_B5 MAKE_GPIO_NUM(PORTB_OFS, 5)#define GPIO_B6 MAKE_GPIO_NUM(PORTB_OFS, 6)#define GPIO_B7 MAKE_GPIO_NUM(PORTB_OFS, 7)#define GPIO_B8 MAKE_GPIO_NUM(PORTB_OFS, 8)#define GPIO_B9 MAKE_GPIO_NUM(PORTB_OFS, 9)#define GPIO_B10 MAKE_GPIO_NUM(PORTB_OFS, 10)#define GPIO_C0 MAKE_GPIO_NUM(PORTC_OFS, 0)#define GPIO_C1 MAKE_GPIO_NUM(PORTC_OFS, 1)#define GPIO_C2 MAKE_GPIO_NUM(PORTC_OFS, 2)#define GPIO_C3 MAKE_GPIO_NUM(PORTC_OFS, 3)#define GPIO_C4 MAKE_GPIO_NUM(PORTC_OFS, 4)#define GPIO_C5 MAKE_GPIO_NUM(PORTC_OFS, 5)#define GPIO_C6 MAKE_GPIO_NUM(PORTC_OFS, 6)#define GPIO_C7 MAKE_GPIO_NUM(PORTC_OFS, 7)#define GPIO_C8 MAKE_GPIO_NUM(PORTC_OFS, 8)#define GPIO_C9 MAKE_GPIO_NUM(PORTC_OFS, 9)#define GPIO_C10 MAKE_GPIO_NUM(PORTC_OFS, 10)#define GPIO_C11 MAKE_GPIO_NUM(PORTC_OFS, 11)#define GPIO_C12 MAKE_GPIO_NUM(PORTC_OFS, 12)#define GPIO_C13 MAKE_GPIO_NUM(PORTC_OFS, 13)#define GPIO_C14 MAKE_GPIO_NUM(PORTC_OFS, 14)#define GPIO_C15 MAKE_GPIO_NUM(PORTC_OFS, 15)#define GPIO_D0 MAKE_GPIO_NUM(PORTD_OFS, 0)#define GPIO_D1 MAKE_GPIO_NUM(PORTD_OFS, 1)#define GPIO_D2 MAKE_GPIO_NUM(PORTD_OFS, 2)⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -