sim_rtl1.log

Coms sensor 的USB 通信程序

ncverilog: 05.10-p004: (c) Copyright 1995-2003 Cadence Design Systems, Inc.
TOOL:	ncverilog	05.10-p004: Started on Aug 09, 2005 at 14:39:58
ncverilog
	+turbo
	+turbo+2
	+turbo+3
	+access+rw
	+incdir+./inc
	+define+Gate+USB+high_speed+ICM_VGA
	+no_notifier
	-l
	sim_rtl.log
	-v
	..//lib/faraday/fs90a_b.lib
	-v
	..//lib/faraday/fs90a_bs.lib
	..//lib/faraday/PLL_CORE.lib
	../mdl/usb_host/fusb_host.v
	..//mdl/i2c/hp_i2c.v
	..//mdl/i2c/i2c_reg.v
	..//mdl/i2c/storage.v
	..//mdl/sensor/icm108b640x480.v
	..//mdl/sensor/icm108b1280x960.v
	..//mdl/sensor/TVencoder.v
	..//mdl/sensor/icm108b64x48.v
	..//mdl/si3000/si3000.v
	..//mdl/ac97/ac97_codec.v
	..//mdl/ac97/ac97_codec_sin.v
	..//mdl/ac97/ac97_codec_sout.v
	..//mdl/si3000/i2s_clkdiv_codec.v
	..//mdl/si3000/i2s_codec.v
	..//mdl/si3000/i2sc.v
	..//mdl/download/mp2_bh.v
	..//mdl/flash/dram_bh.v
	..//mdl/flash/latch_bh.v
	..//mdl/flash/prom_bh.v
	..//mdl/flash/km29u128.vp
	..//mdl/mcu/mcu.v
	/project/cheetah3/asic/lib/smic/smic18.v
	/project/cheetah3/asic/lib/smic/SP018W_V1p4.v
	/project/cheetah3/asic/hdl/chip/ipgoal_phy.vp
	/project/cheetah3/asic/hdl/chip/IPOR_0010E_S_50u.v
	/project/cheetah3/asic/hdl/chip/IVRG_0010E_S.v
	/project/cheetah3/asic/hdl/chip/pulse_gen.v
	/project/cheetah3/asic/hdl/mem/SRAMSP2KX32.v
	/project/cheetah3/asic/lib/DW/DW01_add.v
	/project/cheetah3/asic/lib/DW/DW01_sub.v
	/project/cheetah3/asic/lib/DW/DW01_cmp2.v
	/project/cheetah3/asic/hdl/chip/spare_cell.v
	..//hdl/far/DW01_inc.v
	..//hdl/far/SW101008N04.v
	..//hdl/far/SW103008N03.v
	..//hdl/far/SW208008N04.v
	..//hdl/far/SH002008.v
	..//hdl/far/SU308008.v
	..//hdl/far/SU002808N04.v
	..//hdl/far/SD208008AN.v
	..//hdl/far/TTC_SM32KX8RN.v
	/project/cheetah3/asic/hdl/mem/ram32x16_dp.v
	/project/cheetah3/asic/hdl/mem/ram16x32_dp.v
	..//hdl/far/ram1_mbist.v
	..//hdl/far/ram1_mbist_con.v
	..//hdl/far/ram2_mbist.v
	..//hdl/far/ram2_mbist_con.v
	..//hdl/far/ram3_mbist.v
	..//hdl/far/ram3_mbist_con.v
	..//hdl/far/ram4_mbist.v
	..//hdl/far/ram4_mbist_con.v
	..//hdl/far/ram5_mbist.v
	..//hdl/far/ram5_mbist_con.v
	..//hdl/far/ram6_mbist.v
	..//hdl/far/ram6_mbist_con.v
	..//hdl/far/rom1_mbist.v
	..//hdl/far/rom1_mbist_comp.v
	..//hdl/far/rom1_mbist_top.v
	..//hdl/far/rom1_mbist_con.v
	..//hdl/far/rom2_mbist.v
	..//hdl/far/rom2_mbist_comp.v
	..//hdl/far/rom2_mbist_top.v
	..//hdl/far/rom2_mbist_con.v
	..//hdl/chip/clk_gen.v
	..//hdl/chip/clk_mux.v
	..//hdl/chip/clk_gat.v
	..//hdl/chip/rst_gen.v
	..//hdl/chip/rst_lch.v
	..//hdl/chip/prog_rom.v
	..//hdl/chip/boot_rom.v
	..//hdl/chip/ram320x32.v
	/project/cheetah3/asic/hdl/usb/usb_top.v
	/project/cheetah3/asic/hdl/usb/addr_mod_cal.v
	/project/cheetah3/asic/hdl/usb/crc5.v
	/project/cheetah3/asic/hdl/usb/crc16.v
	/project/cheetah3/asic/hdl/usb/endp0.v
	/project/cheetah3/asic/hdl/usb/endpx.v
	/project/cheetah3/asic/hdl/usb/usb_app.v
	/project/cheetah3/asic/hdl/usb/usb_dma.v
	/project/cheetah3/asic/hdl/usb/usb_endp.v
	/project/cheetah3/asic/hdl/usb/usb_utmi.v
	/project/cheetah3/asic/hdl/usb/usb_pe.v
	/project/cheetah3/asic/hdl/usb/usb_rf.v
	/project/cheetah3/asic/hdl/usb/usb_mcu.v
	/project/cheetah3/asic/hdl/usb/utmi_ls.v
	..//hdl/chip/spare_gate.v
	/project/cheetah3/asic/hdl/app/dbus_ctl.v
	..//hdl/chip/test_count.v
	..//hdl/chip/ir_ctrl.v
	/project/cheetah3/asic/hdl/app/veo_net.v
	..//hdl/uc_intf/uc_reg.v
	..//hdl/uc_intf/uc_intf.v
	..//hdl/v8051/VEO_8051.v
	..//hdl/v8051/v8051_cnt.v
	..//hdl/v8051/v8051_ext_sfr.v
	..//hdl/v8051/v8051_ext_inst.v
	..//hdl/v8051/v8051_ram_256.v
	..//hdl/v8051/v8051_p0.v
	..//hdl/v8051/v8051_p1.v
	..//hdl/v8051/v8051_p2.v
	..//hdl/v8051/v8051_p3.v
	..//hdl/v8051/alu.v
	..//hdl/v8051/DW02_mac.v
	..//hdl/v8051/VEO_DW8051_core.v
	/project/cheetah3/asic/hdl/chip/cheetah_top.v
	/project/cheetah3/asic/hdl/chip/cheetah.v
	/project/cheetah3/asic/mdl/test_bench.v
	..//hdl/audio/si3000_cntl.v
	..//hdl/audio/ac97_ctl.v
	..//hdl/audio/dword_align.v
	..//hdl/audio/sync_ac97.v
	..//hdl/audio/audio_top.v
	..//hdl/audio/i2s_clkdiv.v
	..//hdl/audio/i2s_top.v
	..//hdl/audio/i2s_volumn.v
	..//hdl/audio/i2sc.v
	..//hdl/vcl/vcl.v
	..//hdl/vcl/ccdtg.v
	..//hdl/vcl/ccdtg_top.v
	..//hdl/vcl/avg256.v
	..//hdl/vcl/vcl_top.v
	..//hdl/vcl/sram_ctrl.v
	..//hdl/vcl/sync_high.v
	..//hdl/vcl/bypass_sel.v
	..//hdl/vcl/multiplier.v
	..//hdl/vcl/vcl_yuv.v
	..//hdl/vcl/vclout.v
	..//hdl/vcl/yuv420.v
	..//hdl/vcl/yuv422.v
	..//hdl/vcl/gamma.v
	..//hdl/vcl/detect_lowlight.v
	..//hdl/vcl/vcl_timing.v
	..//hdl/vcl/bt656_det.v
	..//hdl/vcl/spare_vcl.v
	..//hdl/vcl/ram48x24.v
	..//hdl/usb_bulk/bulk_ctrl.v
	..//hdl/usb_bulk/flash_cop.v
	..//hdl/usb_bulk/mp2_cop.v
	..//hdl/usb_bulk/mp2_du.v
	..//hdl/usb_bulk/sync_mp2.v
	..//hdl/usb_bulk/sync_dl.v
	..//hdl/usb_bulk/sync_ul.v
	./test/app_in_fifo.v
	./test/app_out_fifo.v
	..//hdl/i2c/i2c.v
	..//hdl/i2c/cntl_i2c.v
	..//hdl/i2c/i2c_lynx2a.v
	..//hdl/i2c/sdcrc.v
	..//hdl/spi/spiif.v
	..//hdl/spi/spi_top.v
	..//hdl/spi/spiif_8bit.v
	..//hdl/nf_ctl/nfctl.v
	..//hdl/nf_ctl/nfdmactl.v
	..//hdl/regfile/regfile.v
Recompiling... reason: file './dump_mcu.v' is newer than expected.
	expected: Tue Aug  9 14:37:23 2005
	actual:   Tue Aug  9 14:39:55 2005
file: ..//lib/faraday/PLL_CORE.lib
file: ../mdl/usb_host/fusb_host.v
                             //********* 0919.02, Jay **********************************
                               |
ncvlog: *W,NOCMIC (../mdl/usb_host/fusb_host.v,2667|31): error-prone block comment nested within block comment [2.3(IEEE)].
                             //*********************************************************
                               |
ncvlog: *W,NOCMIC (../mdl/usb_host/fusb_host.v,2672|31): error-prone block comment nested within block comment [2.3(IEEE)].
	if(!SPP_SELINN && !EPP_mode) begin	//********************** SPP mode
	                                  	  |
ncvlog: *W,NOCMIC (../mdl/usb_host/fusb_host.v,3198|38): error-prone block comment nested within block comment [2.3(IEEE)].
	else if(SPP_SELINN && !SPP_AUTFDN && !EPP_mode) begin	//****** negotiation mode
	                                                     	  |
ncvlog: *W,NOCMIC (../mdl/usb_host/fusb_host.v,3214|57): error-prone block comment nested within block comment [2.3(IEEE)].
	else if(EPP_mode) begin			//********************** EPP mode
	                       			  |
ncvlog: *W,NOCMIC (../mdl/usb_host/fusb_host.v,3225|29): error-prone block comment nested within block comment [2.3(IEEE)].
	else begin				//********************** Idle
	          				  |
ncvlog: *W,NOCMIC (../mdl/usb_host/fusb_host.v,3263|17): error-prone block comment nested within block comment [2.3(IEEE)].
file: ..//mdl/i2c/hp_i2c.v
file: ..//mdl/i2c/i2c_reg.v
file: ..//mdl/i2c/storage.v
file: ..//mdl/sensor/icm108b640x480.v
file: ..//mdl/sensor/icm108b1280x960.v
file: ..//mdl/sensor/TVencoder.v
file: ..//mdl/sensor/icm108b64x48.v
file: ..//mdl/si3000/si3000.v
file: ..//mdl/ac97/ac97_codec.v
file: ..//mdl/ac97/ac97_codec_sin.v
file: ..//mdl/ac97/ac97_codec_sout.v
file: ..//mdl/si3000/i2s_clkdiv_codec.v
file: ..//mdl/si3000/i2s_codec.v
file: ..//mdl/si3000/i2sc.v
file: ..//mdl/download/mp2_bh.v
file: ..//mdl/flash/dram_bh.v
file: ..//mdl/flash/latch_bh.v
file: ..//mdl/flash/prom_bh.v
file: ..//mdl/flash/km29u128.vp
file: ..//mdl/mcu/mcu.v
file: /project/cheetah3/asic/lib/smic/smic18.v
file: /project/cheetah3/asic/lib/smic/SP018W_V1p4.v
file: /project/cheetah3/asic/hdl/chip/ipgoal_phy.vp
file: /project/cheetah3/asic/hdl/chip/IPOR_0010E_S_50u.v
file: /project/cheetah3/asic/hdl/chip/IVRG_0010E_S.v
file: /project/cheetah3/asic/hdl/chip/pulse_gen.v
file: /project/cheetah3/asic/hdl/mem/SRAMSP2KX32.v
file: /project/cheetah3/asic/lib/DW/DW01_add.v
file: /project/cheetah3/asic/lib/DW/DW01_sub.v
file: /project/cheetah3/asic/lib/DW/DW01_cmp2.v
		 (( is_less(B,A,TC) || A === B ) ? 0'b0 : 1'b1); 

		                                   |
ncvlog: *W,MAXBSZ (/project/cheetah3/asic/lib/DW/DW01_cmp2.v,119|37): zero width prefix to based number ignored [2.5(IEEE)].
file: /project/cheetah3/asic/hdl/chip/spare_cell.v
file: ..//hdl/far/DW01_inc.v
file: ..//hdl/far/SW101008N04.v
  `define    TRUE                 (1'b1)              

                                                      |
ncvlog: *W,MACRDF (..//hdl/far/SW101008N04.v,51|54): text macro 'TRUE' redefined - replaced with new definition.
  `define    FALSE                (1'b0)              

                                                      |
ncvlog: *W,MACRDF (..//hdl/far/SW101008N04.v,52|54): text macro 'FALSE' redefined - replaced with new definition.
file: ..//hdl/far/SW103008N03.v
file: ..//hdl/far/SW208008N04.v
file: ..//hdl/far/SH002008.v
file: ..//hdl/far/SU308008.v
file: ..//hdl/far/SU002808N04.v
file: ..//hdl/far/SD208008AN.v
file: ..//hdl/far/TTC_SM32KX8RN.v
file: /project/cheetah3/asic/hdl/mem/ram32x16_dp.v
file: /project/cheetah3/asic/hdl/mem/ram16x32_dp.v
file: ..//hdl/far/ram1_mbist.v
file: ..//hdl/far/ram1_mbist_con.v
file: ..//hdl/far/ram2_mbist.v
file: ..//hdl/far/ram2_mbist_con.v
file: ..//hdl/far/ram3_mbist.v
file: ..//hdl/far/ram3_mbist_con.v
file: ..//hdl/far/ram4_mbist.v
file: ..//hdl/far/ram4_mbist_con.v
file: ..//hdl/far/ram5_mbist.v
file: ..//hdl/far/ram5_mbist_con.v
file: ..//hdl/far/ram6_mbist.v
file: ..//hdl/far/ram6_mbist_con.v
file: ..//hdl/far/rom1_mbist.v
file: ..//hdl/far/rom1_mbist_comp.v
file: ..//hdl/far/rom1_mbist_top.v
file: ..//hdl/far/rom1_mbist_con.v
file: ..//hdl/far/rom2_mbist.v
file: ..//hdl/far/rom2_mbist_comp.v
file: ..//hdl/far/rom2_mbist_top.v
file: ..//hdl/far/rom2_mbist_con.v
file: ..//hdl/chip/clk_gen.v
file: ..//hdl/chip/clk_mux.v
file: ..//hdl/chip/clk_gat.v
file: ..//hdl/chip/rst_gen.v
file: ..//hdl/chip/rst_lch.v
file: ..//hdl/chip/prog_rom.v
file: ..//hdl/chip/boot_rom.v
file: ..//hdl/chip/ram320x32.v
file: /project/cheetah3/asic/hdl/usb/usb_top.v
file: /project/cheetah3/asic/hdl/usb/addr_mod_cal.v
file: /project/cheetah3/asic/hdl/usb/crc5.v
file: /project/cheetah3/asic/hdl/usb/crc16.v
file: /project/cheetah3/asic/hdl/usb/endp0.v
file: /project/cheetah3/asic/hdl/usb/endpx.v
file: /project/cheetah3/asic/hdl/usb/usb_app.v
file: /project/cheetah3/asic/hdl/usb/usb_dma.v
file: /project/cheetah3/asic/hdl/usb/usb_endp.v
file: /project/cheetah3/asic/hdl/usb/usb_utmi.v
file: /project/cheetah3/asic/hdl/usb/usb_pe.v
parameter[2:0]  

             |
ncvlog: *W,PARRNG (/project/cheetah3/asic/hdl/usb/usb_pe.v,115|13): Range specification on parameter declaration ignored.
parameter[2:0]  

             |
ncvlog: *W,PARRNG (/project/cheetah3/asic/hdl/usb/usb_pe.v,126|13): Range specification on parameter declaration ignored.
parameter[2:0]   

             |
ncvlog: *W,PARRNG (/project/cheetah3/asic/hdl/usb/usb_pe.v,134|13): Range specification on parameter declaration ignored.
file: /project/cheetah3/asic/hdl/usb/usb_rf.v
file: /project/cheetah3/asic/hdl/usb/usb_mcu.v
file: /project/cheetah3/asic/hdl/usb/utmi_ls.v
parameter [2:0]	       // USB20 Emulation State

              |
ncvlog: *W,PARRNG (/project/cheetah3/asic/hdl/usb/utmi_ls.v,84|14): Range specification on parameter declaration ignored.
parameter [2:0]        // USB20 Usb_Reset State

              |
ncvlog: *W,PARRNG (/project/cheetah3/asic/hdl/usb/utmi_ls.v,94|14): Range specification on parameter declaration ignored.
parameter [2:0]        // USB20 Usb_Resume State

              |
ncvlog: *W,PARRNG (/project/cheetah3/asic/hdl/usb/utmi_ls.v,104|14): Range specification on parameter declaration ignored.
file: ..//hdl/chip/spare_gate.v
file: /project/cheetah3/asic/hdl/app/dbus_ctl.v
file: ..//hdl/chip/test_count.v
file: ..//hdl/chip/ir_ctrl.v
file: /project/cheetah3/asic/hdl/app/veo_net.v
file: ..//hdl/uc_intf/uc_reg.v
file: ..//hdl/uc_intf/uc_intf.v
file: ..//hdl/v8051/VEO_8051.v
file: ..//hdl/v8051/v8051_cnt.v
file: ..//hdl/v8051/v8051_ext_sfr.v
file: ..//hdl/v8051/v8051_ext_inst.v
file: ..//hdl/v8051/v8051_ram_256.v
file: ..//hdl/v8051/v8051_p0.v
file: ..//hdl/v8051/v8051_p1.v
file: ..//hdl/v8051/v8051_p2.v
file: ..//hdl/v8051/v8051_p3.v
file: ..//hdl/v8051/alu.v
file: ..//hdl/v8051/DW02_mac.v
file: ..//hdl/v8051/VEO_DW8051_core.v
file: /project/cheetah3/asic/hdl/chip/cheetah_top.v
file: /project/cheetah3/asic/hdl/chip/cheetah.v
file: /project/cheetah3/asic/mdl/test_bench.v
	module worklib.test_bench:v
		errors: 0, warnings: 0
file: ..//hdl/audio/si3000_cntl.v
file: ..//hdl/audio/ac97_ctl.v
file: ..//hdl/audio/dword_align.v
file: ..//hdl/audio/sync_ac97.v
file: ..//hdl/audio/audio_top.v
file: ..//hdl/audio/i2s_clkdiv.v
file: ..//hdl/audio/i2s_top.v
file: ..//hdl/audio/i2s_volumn.v
file: ..//hdl/audio/i2sc.v
file: ..//hdl/vcl/vcl.v
file: ..//hdl/vcl/ccdtg.v
file: ..//hdl/vcl/ccdtg_top.v
file: ..//hdl/vcl/avg256.v
file: ..//hdl/vcl/vcl_top.v
file: ..//hdl/vcl/sram_ctrl.v
file: ..//hdl/vcl/sync_high.v
file: ..//hdl/vcl/bypass_sel.v
file: ..//hdl/vcl/multiplier.v