regfile.txt

Coms sensor 的USB 通信程序

(1) EndpX Transfer & Fifo's Register Defination : 
     a. endp_en   (1 bit)  //Endpoint enable 
        1: Endp is enable
        0: Endp is not enable
     b. endp_dir  (1 bit)  //Endpoint Transfer Direction  
        1: Out transfer
        0: In  transfer 
     c. pkt_xfr_num   (2 bit)  //Transfer Data Pid For ISO 
        00: Sigle  pkt transfer
        01: Double pkt transfer
        10: Triple pkt transfer
        11: Reserved
     d. pkt_size  (11 bit)
        0-1024
     e. endp_type (2 bit)
        00 : Reserve
        01 : ISO   Transfer 
        10 : Bulk  Transfer
        11 : Intr  Transfer
     f. nxt_data_pid[1:0] 
        00 : Data0 --- C3
        01 : Data1 --- 4B
        10 : Data2 --- 87
        11 : DataM --- 0F  
     g. fifo initial address   (13:6) ---- 64 Bytes Jump        
        fifo buffer length     (13:6) ---- 64 Bytes Jump 
        fifo endp rd/wr temp address [13:0]
        fifo appl wr/rd temp address [13:0]
        fifo data count number       [13:0] 
        fifo over  flow    (1 bit)
        fifo under flow    (1 bit) 
     h. fifo_soft_reset    (1 bit)
        endp_ready         (1 bit)
        endp_stall         (1 bit)  
        appl_status        (1 bit)         

 Endpx_conf[31:0]  = { 
                       // 03  
                       endp_buff_depth[7:0]
                       // 02
                       endp_start_addr[7:0] 
                       // 01
                       endp_dir  
                       endp_type   [1:0]         
                       pkt_xfr_numb[1:0]
                       pkt_max_size[10:8]
                       // 00
                       pkt_max_size[7:0] 
                      }
// 04
endp_usb_enable
// endp_soft_reset   /* Reserved */
endp_stall
endp_spk_start   
endp_app_ready
endp_usb_ready
endp_next_dpid[1:0] 
// 06 05
usb_cur_start_addr[13:0]                 
// 08 07
app_cur_start_addr[13:0] 
// 0a 09
fifo_data_count[13:0]
// 0b 0c 0d 0e
Reserved
// 0f
fifo_oflow =  r012f[7]   ;   // fifo over  flow
fifo_uflow =  r012f[6]   ;   // fifo under flow
fifo_bempt =  r012f[5]   ;   // fifo burst empty(can not support a app read transfer)
fifo_bfull =  r012f[4]   ;   // fifo burst full (can not support a app write transfer) 
fifo_nempt =  r012f[3]   ;   // fifo near empty (can not support a usb read transfer) 
fifo_nfull =  r012f[2]   ;   // fifo near full  (can not support a usb wrtie transfer) 
fifo_fempt =  r012f[1]   ;   // fifo fully empty
fifo_ffull =  r012f[0]   ;   // fifo fully full
             
/////////////////////////////////////////////////////
//////// 16 General Purpose Registers   /////////////
/////////////////////////////////////////////////////

00: USB Status Registers
bit7   Hign Speed              // Indicate The device is plug into a high speed host
bit6   usb_have_attach	     // Indicate The device has attached to the host
bit5   usb_normal_mode	     // Indicate The device work in the normal mode
bit4   usb_wakeup_enable	// Indicate The device can go into the wakeup mode
bit3   usb_test_mode	     // Set the USB Control in the test mode
bit2   usb_int_enable	     // Enable Interrupt
bit1   usb_go_suspend	     // Indicate the device is in the suspend mode    
bit0   Soft Reset              // Software reset for the whole usb control 

01: 
     Configuration[7:0]      // Indicated the device's Configuration Value 
                             // Only set_configuration command can change its value

02:  
     Device Address[7:0]     // Indicated the device's Address Value
                             // Only set_address command can change its value
     
03:  VSTA
     (Vendor-Specific Test Mode Status)
     
04: 
[7:5]   test_reg[2:0] 
[4]     Vctload_M
[3:0]   Vctl[3:0]   

05:  Endp 0 Status & Control
bit7     ep0 fifo full    // Endp 0 fifo full
bit6     ep0 fifo empty   // Endp 0 fifo empty 
bit5     ep0 read ready   // Fifo is ready for MCU to read
bit4     ep0 write ready  // Fifo is ready for MCU to write
bit3     ep0 soft reset   //  
bit2     ep0 fifo done    // For Short Packet write transfer
bit1     ep0 fifo stall   // Endp 0 is Stalled 
bit0     ep0 fifo clear   // Flush Endp 0 Fifo

06:  ep0 fifo data count [7:0]

07:  ep0 fifo data port   // For MCU to Access

08: Interrupt Enable 1    // USB  Interrupt Enable bit
 
09: Interrupt Enable 2    // Endp Interrupt Enable bit

0a: Interrupt Enable 3    // Fifo Error Interrupt Enable bit 

0b: Interrupt Enable 4    // Reserved

0c: Interrupt Source 1    // USB  Interrupt Source
bit7     endp0_fifo_err     
bit6     usb_command_err
bit5     usb_resume
bit4     usb_suspend
bit3     usb_reset
bit2     usb_endp0_in
bit1     usb_endp0_out
bit0     usb_endp0_setup    

0d: Interrupt Source 2  // Endp Interrupt Source
bit0     endp1_usb_intr
bit1     endp2_usb_intr
bit2     endp3_usb_intr
bit3     endp4_usb_intr
bit4     endp5_usb_intr
bit5     endp6_usb_intr
bit6     endp7_usb_intr
bit7     endp8_usb_intr

0e: Interrupt Source 3 // Endp Fifo Error Interrupt
bit0     endp1_fifo_err
bit1     endp2_fifo_err
bit2     endp3_fifo_err
bit3     endp4_fifo_err
bit4     endp5_fifo_err
bit5     endp6_fifo_err
bit6     endp7_fifo_err
bit7     endp8_fifo_err 
     
0f: Interrupt Souce 4 // Reserved