sim_rtl25.log

Coms sensor 的USB 通信程序

ncvlog: *W,PARRNG (/project/cheetah3/asic/hdl/usb/utmi_ls.v,94|14): Range specification on parameter declaration ignored.
parameter [2:0]        // USB20 Usb_Resume State

              |
ncvlog: *W,PARRNG (/project/cheetah3/asic/hdl/usb/utmi_ls.v,104|14): Range specification on parameter declaration ignored.
file: ..//hdl/chip/spare_gate.v
	module worklib.spare_gate:v
		errors: 0, warnings: 0
file: /project/cheetah3/asic/hdl/app/dbus_ctl.v
file: ..//hdl/chip/test_count.v
	module worklib.test_count:v
		errors: 0, warnings: 0
file: ..//hdl/chip/ir_ctrl.v
	module worklib.ir_ctrl:v
		errors: 0, warnings: 0
file: /project/cheetah3/asic/hdl/app/veo_net.v
	module worklib.veo_net:v
		errors: 0, warnings: 0
file: ..//hdl/uc_intf/uc_reg.v
	module worklib.uc_reg:v
		errors: 0, warnings: 0
file: ..//hdl/uc_intf/uc_intf.v
	module worklib.uc_intf:v
		errors: 0, warnings: 0
file: ..//hdl/v8051/VEO_8051.v
	module worklib.VEO_8051:v
		errors: 0, warnings: 0
file: ..//hdl/v8051/v8051_cnt.v
	module worklib.v8051_cnt:v
		errors: 0, warnings: 0
file: ..//hdl/v8051/v8051_ext_sfr.v
	module worklib.v8051_ext_sfr:v
		errors: 0, warnings: 0
file: ..//hdl/v8051/v8051_ext_inst.v
	module worklib.v8051_ext_inst:v
		errors: 0, warnings: 0
file: ..//hdl/v8051/v8051_ram_256.v
	module worklib.v8051_ram_256:v
		errors: 0, warnings: 0
file: ..//hdl/v8051/v8051_p0.v
	module worklib.v8051_p0:v
		errors: 0, warnings: 0
file: ..//hdl/v8051/v8051_p1.v
	module worklib.v8051_p1:v
		errors: 0, warnings: 0
file: ..//hdl/v8051/v8051_p2.v
	module worklib.v8051_p2:v
		errors: 0, warnings: 0
file: ..//hdl/v8051/v8051_p3.v
	module worklib.v8051_p3:v
		errors: 0, warnings: 0
file: ..//hdl/v8051/alu.v
	module worklib.alu:v
		errors: 0, warnings: 0
file: ..//hdl/v8051/DW02_mac.v
	module worklib.DW02_mac:v
		errors: 0, warnings: 0
file: ..//hdl/v8051/VEO_DW8051_core.v
	module worklib.VEO_DW8051_updn_ctr_width3_1:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_biu_rom_addr_size13_1:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_alu_DW01_add_9_0:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_alu_DW01_add_5_1:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_alu_DW01_add_5_0:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_alu_DW01_cmp2_8_0:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_alu:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_updn_ctr_width16_1_DW01_incdec_16_1:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_updn_ctr_width16_1_DW01_incdec_16_0:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_updn_ctr_width16_1:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_u_ctr_clr_width2_1:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_op_decoder:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_main_regs_DW01_incdec_8_1:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_main_regs_DW01_incdec_8_0:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_main_regs:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_control:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_cpu_ram_2561_rom_addr_size13_extd_intr1_1_DW01_add_16_0:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_cpu_ram_2561_rom_addr_size13_extd_intr1_1:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_timer_ctr_width8_1_DW01_incdec_8_02:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_timer_ctr_width8_12:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_timer_ctr_width8_1_DW01_incdec_8_03:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_timer_ctr_width8_13:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_timer_ctr_width8_1_DW01_incdec_8_04:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_timer_ctr_width8_14:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_timer_ctr_width8_1_DW01_incdec_8_05:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_timer_ctr_width8_15:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_timer:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_intr_1:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_timer_ctr_width8_1_DW01_incdec_8_00:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_timer_ctr_width8_10:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_timer_ctr_width8_1_DW01_incdec_8_01:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_timer_ctr_width8_11:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_timer2:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_shftreg_width10_11:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_shftreg_width9_11:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_updn_ctr_width4_12:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_updn_ctr_width4_13:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_serial_base_addr152_1:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_shftreg_width10_10:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_shftreg_width9_10:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_updn_ctr_width4_10:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_updn_ctr_width4_11:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_serial_base_addr192_1:v
		errors: 0, warnings: 0
	module worklib.VEO_DW8051_core:v
		errors: 0, warnings: 0
file: /project/cheetah3/asic/hdl/chip/cheetah_top.v
	module worklib.cheetah_top:v
		errors: 0, warnings: 0
file: /project/cheetah3/asic/hdl/chip/cheetah.v
	module worklib.cheetah:v
		errors: 0, warnings: 0
file: /project/cheetah3/asic/mdl/test_bench.v
	module worklib.test_bench:v
		errors: 0, warnings: 0
file: ..//hdl/audio/si3000_cntl.v
	module worklib.si3000_cntl:v
		errors: 0, warnings: 0
file: ..//hdl/audio/ac97_ctl.v
	module worklib.ac97_ctl:v
		errors: 0, warnings: 0
file: ..//hdl/audio/dword_align.v
	module worklib.dword_align:v
		errors: 0, warnings: 0
file: ..//hdl/audio/sync_ac97.v
	module worklib.sync_ac97:v
		errors: 0, warnings: 0
file: ..//hdl/audio/audio_top.v
	module worklib.audio_top:v
		errors: 0, warnings: 0
file: ..//hdl/audio/i2s_clkdiv.v
	module worklib.i2sc_clkdiv:v
		errors: 0, warnings: 0
file: ..//hdl/audio/i2s_top.v
	module worklib.i2sc_top:v
		errors: 0, warnings: 0
file: ..//hdl/audio/i2s_volumn.v
	module worklib.i2sc_volume:v
		errors: 0, warnings: 0
file: ..//hdl/audio/i2sc.v
	module worklib.i2sc:v
		errors: 0, warnings: 0
file: ..//hdl/vcl/vcl.v
	module worklib.vcl:v
		errors: 0, warnings: 0
file: ..//hdl/vcl/ccdtg.v
	module worklib.ccdtg:v
		errors: 0, warnings: 0
file: ..//hdl/vcl/ccdtg_top.v
	module worklib.ccdtg_top:v
		errors: 0, warnings: 0
file: ..//hdl/vcl/avg256.v
	module worklib.avg256:v
		errors: 0, warnings: 0
file: ..//hdl/vcl/vcl_top.v
	module worklib.vcl_top:v
		errors: 0, warnings: 0
file: ..//hdl/vcl/sram_ctrl.v
	module worklib.sram_ctrl:v
		errors: 0, warnings: 0
file: ..//hdl/vcl/sync_high.v
	module worklib.sync_high:v
		errors: 0, warnings: 0
file: ..//hdl/vcl/bypass_sel.v
	module worklib.bypass:v
		errors: 0, warnings: 0
file: ..//hdl/vcl/multiplier.v
	module worklib.mul:v
		errors: 0, warnings: 0
file: ..//hdl/vcl/vcl_yuv.v
	module worklib.vcl_yuv:v
		errors: 0, warnings: 0
file: ..//hdl/vcl/vclout.v
	module worklib.vclout:v
		errors: 0, warnings: 0
file: ..//hdl/vcl/yuv420.v
	module worklib.yuv420:v
		errors: 0, warnings: 0
file: ..//hdl/vcl/yuv422.v
	module worklib.yuv422:v
		errors: 0, warnings: 0
file: ..//hdl/vcl/gamma.v
	module worklib.gamma:v
		errors: 0, warnings: 0
file: ..//hdl/vcl/detect_lowlight.v
	module worklib.detect_lowlight:v
		errors: 0, warnings: 0
file: ..//hdl/vcl/vcl_timing.v
	module worklib.vcltiming:v
		errors: 0, warnings: 0
file: ..//hdl/vcl/bt656_det.v
	module worklib.bt656_det:v
		errors: 0, warnings: 0
file: ..//hdl/vcl/spare_vcl.v
	module worklib.spare_vcl:v
		errors: 0, warnings: 0
file: ..//hdl/vcl/ram48x24.v
	module worklib.ram48x24:v
		errors: 0, warnings: 0
file: ..//hdl/usb_bulk/bulk_ctrl.v
	module worklib.bulk_ctrl:v
		errors: 0, warnings: 0
file: ..//hdl/usb_bulk/flash_cop.v
	module worklib.flash_cop:v
		errors: 0, warnings: 0
file: ..//hdl/usb_bulk/mp2_cop.v
	module worklib.mp2_cop:v
		errors: 0, warnings: 0
file: ..//hdl/usb_bulk/mp2_du.v
	module worklib.mp2_du:v
		errors: 0, warnings: 0
file: ..//hdl/usb_bulk/sync_mp2.v
	module worklib.sync_mp2:v
		errors: 0, warnings: 0
file: ..//hdl/usb_bulk/sync_dl.v
	module worklib.sync_dl:v
		errors: 0, warnings: 0
file: ..//hdl/usb_bulk/sync_ul.v
	module worklib.sync_ul:v
		errors: 0, warnings: 0
file: ./test/app_in_fifo.v
file: ./test/app_out_fifo.v
file: ..//hdl/i2c/i2c.v
	module worklib.i2c:v
		errors: 0, warnings: 0
file: ..//hdl/i2c/cntl_i2c.v
	module worklib.cntl_i2c:v
		errors: 0, warnings: 0
file: ..//hdl/i2c/i2c_lynx2a.v
	module worklib.i2c_lynx2a:v
		errors: 0, warnings: 0
file: ..//hdl/i2c/sdcrc.v
	module worklib.sdcrc:v
		errors: 0, warnings: 0
file: ..//hdl/spi/spiif.v
	module worklib.spiif:v
		errors: 0, warnings: 0
file: ..//hdl/spi/spi_top.v
	module worklib.spi_top:v
		errors: 0, warnings: 0
file: ..//hdl/spi/spiif_8bit.v
	module worklib.spiif_8bit:v
		errors: 0, warnings: 0
file: ..//hdl/nf_ctl/nfctl.v
`define		IDLE			5'h00

       		    			     |
ncvlog: *W,MACRDF (..//hdl/nf_ctl/nfctl.v,81|21): text macro 'IDLE' redefined - replaced with new definition.
	module worklib.nfctl:v
		errors: 0, warnings: 1
file: ..//hdl/nf_ctl/nfdmactl.v
	module worklib.nfdmactl:v
		errors: 0, warnings: 0
file: ..//hdl/regfile/regfile.v
	module worklib.regfile:v
		errors: 0, warnings: 0
file: ..//lib/faraday/fs90a_b.lib
ncvlog: *W,LIBNOU: Library "..//lib/faraday/fs90a_bs.lib" given but not used.
	Total errors/warnings found outside modules and primitives:
		errors: 0, warnings: 1
		Caching library 'worklib' ....... Done
		Caching library 'fs90a_b' ....... Done
	Elaborating the design hierarchy:
    VEO_DW8051_BH_cpu_ram_2561_rom_addr_size13_extd_intr1_1 i_cpu ( .clk(clk), 
                                                                |
ncelab: *W,CUVWSP (../mdl/mcu/mcu.v,26955|64): 1 port was not connected:
	int_rom_cs_n

    VEO_DW8051_BH_biu_rom_addr_size13_1 i_biu ( .clk(clk), .rst_n(rst_out_n), 
                                            |
ncelab: *W,CUVWSP (../mdl/mcu/mcu.v,19373|44): 1 port was not connected:
	int_rom_cs_n

    GTECH_FD2 ale_neg_reg ( .D(n1058), .CP(N979), .CD(1'b1), .Q(ale_neg) );
                        |
ncelab: *W,CUVWSP (../mdl/mcu/mcu.v,2601|24): 1 port was not connected:
	QN

    GTECH_FD2 dec_md_reg ( .D(n1059), .CP(clk), .CD(rst_n), .Q(dec_md) );
                       |
ncelab: *W,CUVWSP (../mdl/mcu/mcu.v,2602|23): 1 port was not connected:
	QN

    GTECH_FD4 md_ld_n_reg ( .D(n1060), .CP(clk), .SD(rst_n), .Q(md_ld_n) );
                        |
ncelab: *W,CUVWSP (../mdl/mcu/mcu.v,2603|24): 1 port was not connected:
	QN

    GTECH_FD2 ram_16bit_access_reg ( .D(n1061), .CP(clk), .CD(rst_n), .Q(N376)
                                 |
ncelab: *W,CUVWSP (../mdl/mcu/mcu.v,2604|33): 1 port was not connected:
	QN

    GTECH_FD2 \bus_seq_reg[0]  ( .D(n1062), .CP(clk), .CD(rst_n), .Q(
                             |
ncelab: *W,CUVWSP (../mdl/mcu/mcu.v,2606|29): 1 port was not connected:
	QN

    GTECH_FD2 \bus_seq_reg[1]  ( .D(n1063), .CP(clk), .CD(rst_n), .Q(
                             |
ncelab: *W,CUVWSP (../mdl/mcu/mcu.v,2608|29): 1 port was not connected:
	QN

    GTECH_FD2 start_ram_seq_reg ( .D(n1064), .CP(clk), .CD(rst_n), .Q(
                              |
ncelab: *W,CUVWSP (../mdl/mcu/mcu.v,2610|30): 1 port was not connected:
	QN

    GTECH_FD2 ram_access_rdy_reg ( .D(n1065), .CP(clk), .CD(rst_n), .Q(
                               |
ncelab: *W,CUVWSP (../mdl/mcu/mcu.v,2612|31): 1 port was not connected:
	QN

    GTECH_FD4 ale_pos_reg ( .D(n1101), .CP(clk), .SD(rst_n), .Q(ale_pos) );
                        |
ncelab: *W,CUVWSP (../mdl/mcu/mcu.v,2684|24): 1 port was not connected:
	QN

    GTECH_FD2 div_res8_reg ( .D(\div_t_res[8] ), .CP(clk), .CD(1'b1), .Q(
                         |
ncelab: *W,CUVWSP (../mdl/mcu/mcu.v,4166|25): 1 port was not connected:
	QN

    VEO_DW8051_BH_alu_DW01_add_9_0 add_318 ( .A({1'b0, a[7], a[6], a[5], a[4], 
                                         |
ncelab: *W,CUVWSP (../mdl/mcu/mcu.v,4168|41): 1 port was not connected: