smi_rw.v

基于IEEE802.3标准的SMII网络通信的VERILOG实现

//******************************************************************************************
//模块名称：		smi_rw
//模块用途：		SMI读写模块
//版本记录：
//v0.10		2006/06/21	
//******************************************************************************************
module smi_rw(
		clk_in, // 要检测的时钟
		resetb, //测试使能
		mdio,
		mdc //
		);
		
input		clk_in;
input		resetb;
inout		mdio;
output		mdc;

wire		clk_in;
wire		resetb;
tri		mdio;
reg		mdc;

reg		smi_idle;          //smi_idle为0表示总线空闲或输入状态
reg		md_out;
reg	[9:0]	smi_ram_addr;
wire	[17:0]	smi_ram_data;
reg	[17:0]	smi_d_r;
reg	[15:0]	smi_d_w;	
reg	[63:0]	smi_shift;	
reg	[6:0]	smi_state_c;
reg		smi_ram_wren;


ram_smi	ram_smi (
	.address ( smi_ram_addr ),
	.clock ( clk_in ),
	.data ( {2'b00,smi_d_w[15:0]} ),
	.wren ( smi_ram_wren ),
	.q ( smi_ram_data )
	);
	
assign	mdio=(smi_idle==1)? smi_shift[63]:1'bz;

always @(posedge clk_in or negedge resetb)
	if(!resetb)
		mdc<=1'b1;
	else	
		mdc<=~mdc;

always @(posedge clk_in or negedge resetb)
	if(!resetb)
		smi_state_c<=0;
	else	
	if(mdc==1'b1&&smi_state_c==70)
		smi_state_c<=0;
	else
	if(mdc==1'b1)
		smi_state_c<=smi_state_c+1;

always @(posedge clk_in or negedge resetb)
	if(!resetb)
		smi_shift<=0;
	else	
	if(mdc==1'b1)
		begin
			if(smi_state_c==0)
				smi_shift<={34'h3FFFFFFFD,~smi_d_r[16],smi_d_r[16],smi_ram_addr,2'b10,smi_d_r[15:0]};
			else
				smi_shift<={smi_shift[62:0],smi_shift[63]};
		end


always @(posedge clk_in or negedge resetb)
	if(!resetb)
		smi_d_r<=0;
	else	
	if(mdc==1'b1&&smi_state_c==68)
		smi_d_r<=smi_ram_data;

always @(posedge clk_in or negedge resetb)
	if(!resetb)
		smi_ram_addr<=0;
	else	
	if(mdc==1'b1&&smi_state_c==65)
		smi_ram_addr<=smi_ram_addr+1;		

always @(posedge clk_in or negedge resetb)
	if(!resetb)
		smi_ram_wren<=0;
	else	
	if(mdc==1'b0&&smi_state_c==64)
		smi_ram_wren<=smi_d_r[17]&(~smi_d_r[16]);	
	else
		smi_ram_wren<=1'b0;

	
	
always @(posedge clk_in or negedge resetb)
	if(!resetb)
		smi_d_w<=0;
	else	
	if(mdc==1'b0)
		begin
			if(smi_state_c>48&&smi_state_c<=64)
				smi_d_w[15:0]<={smi_d_w[14:0],mdio};
		end

always @(posedge clk_in or negedge resetb)
	if(!resetb)
		smi_idle<=0;
	else
	if(mdc==1'b1)
	begin
		if(smi_state_c>=64)
			smi_idle<=0;
		else
		if((smi_d_r[16]==1'b0)&&(smi_state_c==46||(smi_state_c>47&&smi_state_c<64)))
			smi_idle<=0;
		else
			smi_idle<=smi_d_r[17];
	end
		
endmodule