📄 initializes.lst
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129 1 // 01: DAC output updates occur on Timer 3 overflow.
130 1 // 10: DAC output updates occur on Timer 4 overflow.
131 1 // 11: DAC output updates occur on Timer 2 overflow.
132 1 // Bits2-0: DAC0DF2-0: DAC0 Data Format Bits:
133 1 // 000: The most significant nibble of the DAC0 Data Word is in DAC0H[3:0],
134 1 // while the least significant byte is in DAC0L.
135 1 // 001: The most significant 5-bits of the DAC0 Data Word is in DAC0H[4:0],
136 1 // while the least significant 7-bits are in DAC0L[7:1].
137 1 // 010: The most significant 6-bits of the DAC0 Data Word is in DAC0H[5:0],
138 1 // while the least significant 6-bits are in DAC0L[7:2].
139 1 // 011: The most significant 7-bits of the DAC0 Data Word is in DAC0H[6:0],
140 1 // while the least significant 5-bits are in DAC0L[7:3].
141 1 // 1xx: The most significant 8-bits of the DAC0 Data Word is in DAC0H[7:0],
142 1 // while the least significant 4-bits are in DAC0L[7:4].
143 1
144 1 //------------------------------------------------------------------------------------
145 1 // DAC1_Init
146 1 //------------------------------------------------------------------------------------
147 1 // Configure DAC1 to DAC output updates occur on a write to DAC1H.
148 1 //
149 1 //
150 1 DAC1CN = 0x80; // DAC1CN: DAC1 Enable, Output updates occur on a write to DAC1H.
151 1 //
152 1 // Bit 7: DAC1EN : DAC1 Enable Bit.
153 1 // Bits4-3: DAC1MD1-0: DAC1 Mode Bits.
154 1 // 00: DAC output updates occur on a write to DAC1H.
155 1 // 01: DAC output updates occur on Timer 3 overflow.
156 1 // 10: DAC output updates occur on Timer 4 overflow.
157 1 // 11: DAC output updates occur on Timer 2 overflow.
158 1 // Bits2-0: DAC1DF2-0: DAC1 Data Format Bits:
159 1 // 000: The most significant nibble of the DAC1 Data Word is in DAC1H[3:0],
160 1 // while the least significant byte is in DAC1L.
161 1 // 001: The most significant 5-bits of the DAC1 Data Word is in DAC1H[4:0],
162 1 // while the least significant 7-bits are in DAC1L[7:1].
163 1 // 010: The most significant 6-bits of the DAC1 Data Word is in DAC1H[5:0],
164 1 // while the least significant 6-bits are in DAC1L[7:2].
165 1 // 011: The most significant 7-bits of the DAC1 Data Word is in DAC1H[6:0],
166 1 // while the least significant 5-bits are in DAC1L[7:3].
167 1 // 1xx: The most significant 8-bits of the DAC1 Data Word is in DAC1H[7:0],
168 1 // while the least significant 4-bits are in DAC1L[7:4].
169 1
170 1 //-------------------------------------------------------------------------------------------------
171 1 // Init Enable
172 1 //-------------------------------------------------------------------------------------------------
173 1 EA = 1; // Global interrupt enable
174 1
175 1 // ET2 = 1; // Enable Timer 2 Interrupt. ( )
176 1 // ES0 = 1; // Enable UART0 Interrupt. ( )
177 1 ET1 = 1; // Enable Timer 1 Interrupt. ( )
178 1 // EX1 = 1; // Enable External Interrupt 1. ( )
179 1 // ET0 = 1; // Enable Timer 0 Interrupt. ( )
C51 COMPILER V7.20 INITIALIZES 11/15/2005 18:46:53 PAGE 4
180 1 // EX0 = 1; // Enable External Interrupt 0. ( )
181 1
182 1 // EIE1 |= 0x80; // ECP1R: Enable Comparator1 (CP1) Rising Edge Interrupt.
183 1 // EIE1 |= 0x40; // ECP1F: Enable Comparator1 (CP1) Falling Edge Interrupt.
184 1 // EIE1 |= 0x20; // ECP0R: Enable Comparator0 (CP0) Rising Edge Interrupt.
185 1 // EIE1 |= 0x10; // ECP0F: Enable Comparator0 (CP0) Falling Edge Interrupt.
186 1 // EIE1 |= 0x08; // EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.
187 1 // EIE1 |= 0x04; // EWADC0:Enable Window Comparison ADC0 Interrupt.
188 1 // EIE1 |= 0x02; // ESMB0: Enable System Management Bus (SMBus0) Interrupt.
189 1 // EIE1 |= 0x01; // ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.
190 1
191 1 // EIE2 |= 0x80; // EXVLD: Enable External Clock Source Valid (XTLVLD) Interrupt.
192 1 // EIE2 |= 0x40; // ES1: Enable UART1 Interrupt.
193 1 // EIE2 |= 0x20; // EX7: Enable External Interrupt 7.
194 1 EIE2 |= 0x10; // EX6: Enable External Interrupt 6.
195 1 // EIE2 |= 0x08; // EADC1: Enable ADC1 End Of Conversion Interrupt.
196 1 // EIE2 |= 0x04; // ET4: Enable Timer 4 Interrupt
197 1 // EIE2 |= 0x02; // EADC0: Enable ADC0 End of Conversion Interrupt.
198 1 // EIE2 |= 0x01; // ET3: Enable Timer 3 Interrupt.
199 1
200 1 //-------------------------------------------------------------------------------------------------
201 1 // Timer Init
202 1 //-------------------------------------------------------------------------------------------------
203 1 // Clock Control Register
204 1 CKCON = 0x00; // 0: Timer uses the system clock divided by 12.
205 1 // 1: Timer uses the system clock.
206 1 //-----------------------------------------------------
207 1 // Bit6: T4M: Timer 4 Clock Select.
208 1 // Bit5: T2M: Timer 2 Clock Select.
209 1 // Bit4: T1M: Timer 1 Clock Select.
210 1
211 1 // Bit3: T0M: Timer 0 Clock Select.
212 1 // Bits2-0: Reserved. Read = 000b, Must Write = 000.
213 1
214 1
215 1 //------------------------------------------------------------------------------------
216 1 // Timer0_Init
217 1 //------------------------------------------------------------------------------------
218 1 // Configure Timer0 to auto-reload and generate an interrupt at interval
219 1 // using SYSCLK/12 as its time base.
220 1 // (For PCA)
221 1 TMOD |= 0x02; // TMOD: Timer 0, Mode 2, 8-bit Reload.
222 1 //
223 1 // Bit3 : GATE0 : Timer 0 Gate Control.
224 1 // Bit2 : C/T0 : Counter/Timer 0 Select.
225 1 // Bits1-0: T0M1-T0M0: Timer 0 Mode Select.
226 1 TH0 = 100;
227 1
228 1 // CKCON |= 0x08; // (CKCON.3) Timer0 uses SYSCLK as time base
229 1
230 1 TR0 = 1; // Start Timer0
231 1
232 1 //------------------------------------------------------------------------------------
233 1 // Timer1_Init
234 1 //------------------------------------------------------------------------------------
235 1 // Configure Timer1 to auto-reload and generate an interrupt at interval
236 1 // using SYSCLK/12 as its time base.
237 1 // ( For Car )
238 1 TMOD |= 0x60; // TMOD: Counter 1, Mode 2, 8-bit Reload
239 1 //
240 1 // Bit7 : GATE1 : Timer 1 Gate Control.
241 1 // Bit6 : C/T1 : Counter/Timer 1 Select.
C51 COMPILER V7.20 INITIALIZES 11/15/2005 18:46:53 PAGE 5
242 1 // Bits5-4: T1M1-T1M0: Timer 1 Mode Select.
243 1 TH1 = 255; //
244 1 TL1 = 255;
245 1
246 1 PT1 = 1; // Prior
247 1
248 1 TR1 = 1; // Start Timer1
249 1
250 1
251 1 //------------------------------------------------------------------------------------
252 1 // Timer2_Init
253 1 //------------------------------------------------------------------------------------
254 1 // Configure Timer2 to auto-reload and generate an interrupt at interval
255 1 // using SYSCLK/12 as its time base.
256 1 // ( For UART0 )
257 1 T2CON = 0x30; // Stop Timer2; Clear TF2; Baud rate generator for UART0
258 1 //
259 1 // Bit7: TF2: Timer 2 Overflow Flag.
260 1 // Bit6: EXF2: Timer 2 External Flag.
261 1 // Bit5: RCLK0: Receive Clock Flag for UART0.
262 1 // Bit4: TCLK0: Transmit Clock Flag for UART0.
263 1 // Bit3: EXEN2: Timer 2 External Enable.
264 1 // Bit2: TR2: Timer 2 Run Control.
265 1 // Bit1: C/T2: Counter/Timer Select.
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