iai_ezmac_plus_internal.c

Integration的EZMac Plus

					}
					else
					{
					 Data = (EZ_reg.bytes.SIDB & 0x0F) << 4;
					 Data += EZ_reg.bytes.DIDB & 0x0F;
					}
            }
         else
            {
            //normal address mode or reduced network address mode -> 8 bit address is copied from the SID register
				if(EZ_state == EZMac_S_SendingAck) //EzMacPlus
					 Data = EZ_reg.bytes.DIDB; // For ACK sending we need to swap the DID and the SID
					else
					 Data = EZ_reg.bytes.SIDB; // For ACK sending we need to swap the DID and the SID
            }
         }	  
      //calc CRC for this byte
      Crc_On_Fly(Data);
    break;

 /*Send the EzMacPlus Control byte...*/
   case EZ_TxSendControl:
      if( It_Source == IT_SOURCE_T1 )
         {//SW Watchdog timer overrun -> Trixie HW error
         _TrixieHWError();
         return;
		 }

	//write byte (Data1) to the trixie
      #ifdef SM_REAL_FUNCTION
       _WriteByte_Trixie (Data1);
      #endif
      //save the previosly calculated data byte
      Data1 = Data;
      //next state
	   EZInternalState = EZ_TxSendHeader1;	  
	   
      //what can be the second header byte (H2)?
      if( EZ_reg.bits.MCRB.CIDEN )
         {//CID is used
         if( EZ_reg.bits.MCRB.RAR && !(EZ_reg.bits.MCRB.NWAD) )
            {//reduced address mode and not network address -> 8 bit address is copied from lower nibble of the SID and DID registers
               if(EZ_state == EZMac_S_SendingAck) //EzMacPlus
					{// For ACK sending we need to swap the DID and the SID
					 Data = (EZ_reg.bytes.DIDB & 0x0F) << 4;
					 Data += EZ_reg.bytes.SIDB & 0x0F;
					}
					else
					{
					 Data = (EZ_reg.bytes.SIDB & 0x0F) << 4;
					 Data += EZ_reg.bytes.DIDB & 0x0F;
					}
            }
         else
            {
            //normal address mode or reduced network address mode -> 8 bit address is copied from the SID register
				if(EZ_state == EZMac_S_SendingAck) //EzMacPlus
					 Data = EZ_reg.bytes.DIDB; // For ACK sending we need to swap the DID and the SID
					else
					 Data = EZ_reg.bytes.SIDB; // For ACK sending we need to swap the DID and the SID
            }
         }
      else
         {//CID is not used
         if( EZ_reg.bits.MCRB.RAR )
            {//reduced address mode
            if( EZ_reg.bits.MCRB.DNPL )
			   {
               //dynamic packet length
				   if(EZ_state == EZMac_S_SendingAck) //EzMacPlus
							Data = 1;	// The ack packet is 1 byte length
						else
							Data = EZ_reg.bytes.PLENB;
			   }
            else
               {//fix packet length
			   if(EZ_state == EZMac_S_SendingAck) //EzMacPlus
						Data = 0;
					else
						Data = EZ_reg.bytes.DBuff[DataByteCounter];
						
               DataByteCounter++;
               EZInternalState = EZ_TxSendData;
               }
            }
         else
			{
            //normal address mode
				if(EZ_state == EZMac_S_SendingAck) //EzMacPlus
					 Data = EZ_reg.bytes.SIDB; // For ACK sending we need to swap the DID and the SID
					else
					 Data = EZ_reg.bytes.DIDB; // For ACK sending we need to swap the DID and the SID
			}
         }
      //calc CRC for this byte
      Crc_On_Fly(Data);
      //the CRC was calculated for all of the databytes
         if(DataByteCounter == EZ_reg.bytes.PLENB) 
         {
         EZInternalState = EZ_TxCalcCrc;
         DataByteCounter = 1;
         }
    
   break;
   


 /*Send the 1. header byte...*/
   case EZ_TxSendHeader1:
      if( It_Source == IT_SOURCE_T1 )
         {//SW Watchdog timer overrun -> Trixie HW error
         _TrixieHWError();
         return;
         }
      //write byte (Data1) to the trixie
      #ifdef SM_REAL_FUNCTION
       _WriteByte_Trixie (Data1);
      #endif
      //save the previosly calculated data byte
      Data1 = Data;
      //next state
      EZInternalState = EZ_TxSendHeader2;
      //what can be the 3d header byte (H3)?
      if( EZ_reg.bits.MCRB.CIDEN )
         {//CID is used
         if( EZ_reg.bits.MCRB.RAR )
            {//reduced address mode
            if( EZ_reg.bits.MCRB.DNPL )
				{
               //dynamic packet length
               if(EZ_state == EZMac_S_SendingAck) //EzMacPlus
							Data = 1;	// The ack packet is 1 byte length
						else
							Data = EZ_reg.bytes.PLENB;
				}
            else
               {//fix packet length
			   if(EZ_state == EZMac_S_SendingAck) //EzMacPlus
						Data = 0;
					else
						Data = EZ_reg.bytes.DBuff[DataByteCounter];
			   
               DataByteCounter++;
               EZInternalState = EZ_TxSendData;
               }
            }
         else
			{
			//normal address mode
			if(EZ_state == EZMac_S_SendingAck) //EzMacPlus
					 Data = EZ_reg.bytes.SIDB; // For ACK sending we need to swap the DID and the SID
					else
					 Data = EZ_reg.bytes.DIDB; // For ACK sending we need to swap the DID and the SID
			}
         }
      else
         {//CID is not used
         if( EZ_reg.bits.MCRB.RAR )
            {//reduced address mode
            if(EZ_state == EZMac_S_SendingAck) //EzMacPlus
						Data = 0;
					else
						Data = EZ_reg.bytes.DBuff[DataByteCounter];
						
            DataByteCounter++;
            EZInternalState = EZ_TxSendData;
            }
         else
            {//normal address mode
            if( EZ_reg.bits.MCRB.DNPL )
               {
               //dynamic packet length
               if(EZ_state == EZMac_S_SendingAck) //EzMacPlus
							Data = 1;	// The ack packet is 1 byte length
						else
							Data = EZ_reg.bytes.PLENB;
				}
            else
               {//fix packet length
			   if(EZ_state == EZMac_S_SendingAck) //EzMacPlus
						Data = 0;
					else
						Data = EZ_reg.bytes.DBuff[DataByteCounter];
						
               DataByteCounter++;
               EZInternalState = EZ_TxSendData;
               }
            }
         }

      //calc CRC for this byte
      Crc_On_Fly(Data);
      //the CRC was calculated for all of the databytes
      if( (DataByteCounter == EZ_reg.bytes.PLENB) || ((EZ_state == EZMac_S_SendingAck)&&(EZ_reg.bits.MCRB.DNPL)&&(DataByteCounter)) )
         {
         EZInternalState = EZ_TxCalcCrc;
         DataByteCounter = 1;
         }
   break;

 /*Send the 2. header byte*/
   case EZ_TxSendHeader2:
      if( It_Source == IT_SOURCE_T1 )
         {//SW Watchdog timer overrun -> Trixie HW error
         _TrixieHWError();
         return;
         }
      //write byte (Data1) to the trixie
      #ifdef SM_REAL_FUNCTION
       _WriteByte_Trixie (Data1);
      #endif
      //save the previosly calculated data byte
      Data1 = Data;
      //next state
      EZInternalState = EZ_TxSendData;
      //what can be the 4d header byte (H4)?
      if( EZ_reg.bits.MCRB.CIDEN && EZ_reg.bits.MCRB.DNPL && !EZ_reg.bits.MCRB.RAR)
         {
           //dynamic packet length
           if(EZ_state == EZMac_S_SendingAck) //EzMacPlus
						Data = 1;	// The ack packet is 1 byte length in dynamic address mode
					else
						Data = EZ_reg.bytes.PLENB;
		}
      else
         {//fix packet length
		 if(EZ_state == EZMac_S_SendingAck) //EzMacPlus
						Data = 0;
					else
						Data = EZ_reg.bytes.DBuff[DataByteCounter];
         
         DataByteCounter++;
         EZInternalState = EZ_TxSendData;
         }
      //calc CRC for this byte
      Crc_On_Fly(Data);
      //the CRC was calculated for all of the databytes
      if( (DataByteCounter == EZ_reg.bytes.PLENB) || ((EZ_state == EZMac_S_SendingAck)&&(EZ_reg.bits.MCRB.DNPL)&&(DataByteCounter)) )
         {
         EZInternalState = EZ_TxCalcCrc;
         DataByteCounter = 1;
         }
   break;

 /*Send the data bytes*/
   case EZ_TxSendData:
      if( It_Source == IT_SOURCE_T1 )
         {//SW Watchdog timer overrun -> Trixie HW error
         _TrixieHWError();
         return;
         }
      //write byte (Data1) to the trixie
      #ifdef SM_REAL_FUNCTION
       _WriteByte_Trixie (Data1);
      #endif
      //save the previosly calculated data byte
      Data1 = Data;
      //the new data byte
	  if(EZ_state == EZMac_S_SendingAck) //EzMacPlus
						Data = 0;
					else
						Data = EZ_reg.bytes.DBuff[DataByteCounter];
      
      DataByteCounter++;
      //Calc CRC
      Crc_On_Fly(Data);
      if( (DataByteCounter == EZ_reg.bytes.PLENB) || ((EZ_state == EZMac_S_SendingAck)&&(EZ_reg.bits.MCRB.DNPL)&&(DataByteCounter)) )
         {
         EZInternalState = EZ_TxCalcCrc;
         DataByteCounter = 1;
         }
   break;

 /*Send the data bytes, calc the CRC for the CRC bytes (0x00)*/
   case EZ_TxCalcCrc:
      if( It_Source == IT_SOURCE_T1 )
         {//SW Watchdog timer overrun -> Trixie HW error
         _TrixieHWError();
         return;
         }
      //write byte (Data1) to the Trixie
      #ifdef SM_REAL_FUNCTION
       _WriteByte_Trixie (Data1);
      #endif
      //calc CRC
      Crc_On_Fly(0x00);
      //save the previosly calculated data byte
      Data1 = Data;
      EZInternalState = EZ_TxCalcCrc1;
   break;

 /*Send the last data byte, calc the CRC*/
   case EZ_TxCalcCrc1:
      if( It_Source == IT_SOURCE_T1 )
         {//SW Watchdog timer overrun -> Trixie HW error
         _TrixieHWError();
         return;
         }
      //write byte (Data1) to the Trixie
      #ifdef SM_REAL_FUNCTION
       _WriteByte_Trixie (Data1);
      #endif
      //calc CRC
      Crc_On_Fly(0x00);
      //set the last 2 bytes
      Data = EZ_crc.bytes[0].adat;
      Data1 = EZ_crc.bytes[1].adat;
      EZInternalState = EZ_TxSendEdc;
      //One byte more should be copied to the FIFO to send the last byte correctly
      DataByteCounter = 2;
   break;

 /*Send the CRC bytes*/
   case EZ_TxSendEdc:
      if( It_Source == IT_SOURCE_T1 )
         {//SW Watchdog timer overrun -> Trixie HW error
         _TrixieHWError();
         return;
         }
      //write byte (Data1) to the trixie
      #ifdef SM_REAL_FUNCTION
       _WriteByte_Trixie (Data1);
      #endif
      Data1 = Data;
      if( DataByteCounter == 0 )
         //it was the last byte, end of Tx
         EZInternalState = EZ_TxEnd;
      else
         DataByteCounter--;
   break;

 /*End of the transmit*/
   case EZ_TxEnd:
      if( It_Source == IT_SOURCE_T1 )
         {//SW Watchdog timer overrun -> Trixie HW error
         _TrixieHWError();
         return;
         }
      //turn off Trixie and go to Idle or Sleep state (depend on AXOT bit)
	  if( (EZ_state == EZMac_S_SendingAck) || (EZ_state == EZMac_S_Forwarding) )
			{
				// We have sended an ACK, switch of the Radio, and signal that an incoming packet receive is complet.
				//disable all interrupts
				#ifdef LED_DEBUG
				LED3 = 1;
				#endif
				_Turn_Off_Timer1();
				disable_interrupts(INT_EXT);
				
				 #ifdef SM_REAL_FUNCTION
					EZ_commands.arr[Config_command]=0x8000 | FREQ_Band | XTAL_COMP;  //switch off TX latch, and RX FIFO
					EZRadio_Write(EZ_commands.arr[Config_command]);
					EZ_commands.arr[Power_command] &= 0xff0f;	// switch of the radio
					EZRadio_Write(EZ_commands.arr[Power_command]);
					EZRadio_Statusread ();                     //reset all non latched IT in Trixie
				#endif
				#ifdef LED_DEBUG
				LED4 = 1;
				#endif
				
				if ( (EZ_state == EZMac_S_Forwarding) && (StateAfterForward != EZMac_S_PacketValid))
					{
					    #ifdef ARSSI_USED
						    setup_adc(ADC_CLOCK_DIV_32);
						    set_adc_channel(ARSSI_CHANNEL);
					    #endif					  

						//configure Trixie
					    #ifdef SM_REAL_FUNCTION
						    EZ_commands.arr[Config_command]=0x8000 | FREQ_Band | XTAL_COMP | FIFO_USED;  //switch on RX FIFO
						    EZRadio_Write(EZ_commands.arr[Config_command]);
						    EZRadio_Statusread ();
						    EZ_commands.arr[Power_command] |= 0x0080;                                    //switch on the receiver
						    EZRadio_Write(EZ_commands.arr[Power_command]);
					    #endif

						 //set the frequency
					     Frequency = EZ_reg.bits.RCRB.RF;

					     //setup T1 to wake up the state machine (Ch_Check_Start in IAI_EZmac_internal.c will do)
						 Ch_Check_Start(TRUE);
						 //next states will not read data bytes -> Interrupt routine should set the SPI select pin
						 SetSpiEn = TRUE;
						 //parameters for channel check
						 Data = 0;
						 Data1 = 0;
					}
					else
					{
						EZ_state = EZMac_S_PacketValid;	//Signal that the packet is ready
						EZInternalState = EZ_RxEnd;
					}
			}
		else