iai_ezmac_plus_internal.c

Integration的EZMac Plus

			FirstError = TRUE;
         }
         else
         {//DQD was logic low more than twice -> no valid FSK data
			if(EZ_state == EZMac_S_WaitingForAck)
				 EZMac_Ackwait(1);
			else
				 Ch_Check_Start(TRUE);
         }
      }
      else
      {
         //Start Timer1 -> read next sample of DQD
         _Set_Timer1(DQD_TIMER_LIMIT);
      }
   break;
   
  /*Reciving the control byte*/
   case EZ_RxCheckControl:
	   if( It_Source == IT_SOURCE_T1 )
			 {                          //Timer IRQ -> CRL checking
				if (Data)               //cycle counter, check CRL until {Packet_Start_Timeout="number of preambles+3" (2D D4 and the first data byte)} ms
				{                       // in every ms
				   Data--;
				SEL_PIN = 0;
				Spi_Comm0();
				CLK_PIN = 1;                           //go to the CRL bit (previously we were at DQD bit in the status)
				CLK_PIN = 0;
	
				   if (MISO_PIN)      //Test Clock Recovery locked bit
				   {
					  _Set_Timer1( 65535 - (CRL_CHECK_TIMER_LIMIT) );           //next round
					  SEL_PIN = 1;
					  break;
				   }
				}
				//No clock recovery, we are receiving an FSK signal which is not sent for us, or the Packet_Start_Timeout ended. -> go away!
				//if the error counter of ... is enabled, then increment it
				SEL_PIN = 1;
				if( !FirstError && EZ_reg.bits.EDCRB.SPM && (EZ_reg.bytes.EC[Frequency] < 255) )
				   EZ_reg.bytes.EC[Frequency]++;
				//if the error counter of Tx-Rx sync. is enabled, then increment it
				if( FirstError && EZ_reg.bits.EDCRB.TRSY && (EZ_reg.bytes.EC[Frequency] < 255) )
				{
				   EZ_reg.bytes.EC[Frequency]++;
				   FirstError = FALSE;
				}
				//go to the next channel or keep waiting in the same channel if we are waiting for ACK
				if(EZ_state == EZMac_S_WaitingForAck)
				 EZMac_Ackwait(10);
				else
				 Ch_Check_Start(TRUE);
			 }
		  else
			 {//EzMacPlus Control byte is in the FIFO
			  //set the Soft WDTimer for RX
			  #ifdef SM_SOFTWDT_EN
			  //enable the software watchdog timer for receiving
			  _Set_Timer1(MAX_RX_PACKET_TIMER);
			  #endif
			  //read the data from the Trixie (Data)
			  #ifdef SM_REAL_FUNCTION
			  Data = _ReadByte_Trixie();
			  #else
			  Data = 0x01;            //only for test
			  #endif

     		  ControlField = Data;
			  //Check the Control byte
			 
			  if(EZ_state != EZMac_S_WaitingForAck)
					if((ControlField & 0x04) && (!(EZ_reg.bits.MCRB.NWAD)))	//Is ACK needed, we can't send ACK in network address mode
						AckNeeded = 1;
					else
						AckNeeded = 0;				
	
			  //Calc CRC
			  Crc_On_Fly(Data);
				 
			  //Set next state
			  if( EZ_reg.bits.MCRB.CIDEN )
					EZInternalState = EZ_RxCheckCID; 	//CID byte is used
				else
					EZInternalState = EZ_RxCheckSID;	//CID byte isn't used
			
			  if(EZ_state != EZMac_S_WaitingForAck)
					EZ_state = EZMac_S_Receiving;		
			 }
   break;

 /*receiving the first byte*/
   case EZ_RxCheckCID:
     if( It_Source == IT_SOURCE_T1 )
         //SW Watchdog timer overrun -> Trixie HW error
         _TrixieHWError();
      else
         {//CID is in the FIFO
         //set the Soft WDTimer for RX
         #ifdef SM_SOFTWDT_EN
          //enable the software watchdog timer for receiving
          _Set_Timer1(MAX_RX_PACKET_TIMER);
         #endif
         //read the data from the Trixie (Data)
         #ifdef SM_REAL_FUNCTION
          Data = _ReadByte_Trixie();
         #else
          Data = 0xCD;            //only for test
         #endif
         //check the CID
         if( ((EZ_reg.bits.PFCRB.CFEN && (Data == EZ_reg.bytes.CIDB)) || (!EZ_reg.bits.PFCRB.CFEN)) || EZ_reg.bits.PFCRB.PREN )
            {
            //save the byte
            EZ_reg.bytes.RX_CIDB = Data;
            EZInternalState = EZ_RxCheckSID;
            //Calc CRC
            Crc_On_Fly(Data);
            }
         else
            {
            //inc the error counter
            if( EZ_reg.bits.EDCRB.BCID && (EZ_reg.bytes.EC[Frequency] < 255))
               EZ_reg.bytes.EC[Frequency]++;
            //go to the next freq.
			if(EZ_state == EZMac_S_WaitingForAck)
				 EZMac_Ackwait(12);
			else
				 Ch_Check_Start(TRUE);
            }
         }
   break;

 /*receiving the first or second byte*/
   case EZ_RxCheckSID:
    if( It_Source == IT_SOURCE_T1 )
         //SW Watchdog timer overrun -> Trixie HW error
         _TrixieHWError();
      else
         {//SID received, read the data from the Trixie (Data)
         #ifdef SM_REAL_FUNCTION
          Data = _ReadByte_Trixie();
         #else
          Data = 0xF1;
         #endif
         //if it is the first header byte, then activate the SW watch dog timer for receiving
         #ifdef SM_SOFTWDT_EN
          if(!EZ_reg.bits.MCRB.CIDEN)
             _Set_Timer1(MAX_RX_PACKET_TIMER);
         #endif
         //check the SID
         AddrSID = FALSE;
         AddrDID = FALSE;
         if( EZ_reg.bits.MCRB.RAR )
            {//reduced address is used
            if( EZ_reg.bits.MCRB.NWAD )
               {//network address mode, not that ack is not possible in this mode
			    //DID filter
               if( !EZ_reg.bits.PFCRB.DFEN )
                  AddrSID = TRUE;
               //network address filter
               if( EZ_reg.bytes.SFLTNIDL == Data )
                  AddrSID = TRUE;
               //broadcast filter
               if( EZ_reg.bits.PFCRB.BCEN && ( Data == 0xFF ))
				  {
                  AddrSID = TRUE;
                  EZ_reg.bits.RSRB.BCA = 1;		
			 	  }	
               if( AddrSID || EZ_reg.bits.PFCRB.PREN )
                  {
                  //save the data
                  EZ_reg.bytes.SIDB = Data;
                  AddrDID = TRUE;
                  }
               }
            else
               {//not network address mode
               //SID filter
               if( (EZ_reg.bits.PFCRB.SFEN && ( ((EZ_reg.bytes.SFLTNIDL & 0x0F) & (EZ_reg.bytes.SMSKNIDH & 0x0F)) ==
               (((Data & 0xF0)>>4) & (EZ_reg.bytes.SMSKNIDH & 0x0F)) )) || !EZ_reg.bits.PFCRB.SFEN )
                  {
				  	//save the byte
					EZ_reg.bytes.SIDB = (Data & 0xF0) >> 4;
					AddrSID = TRUE;					
                  }
               //DID filter
               if( !EZ_reg.bits.PFCRB.DFEN )
                  AddrDID = TRUE;
               //self address filter
               if( (Data & 0x0F) == (EZ_reg.bytes.SFIDB & 0x0F) )
                  {
                  EZ_reg.bits.RSRB.SELFA = 1;
                  AddrDID = TRUE;
                  }
               //broadcast filter
               if( EZ_reg.bits.PFCRB.BCEN && ((Data & 0x0F) == 0x0F) )
                  {
                  EZ_reg.bits.RSRB.BCA = 1;
                  AddrDID = TRUE;
                  }
               //multicast address mode filter
               if( EZ_reg.bits.PFCRB.MCFEN && EZ_reg.bits.PFCRB.ApnM && ((EZ_reg.bytes.MCAMCM & 0x0F) == (Data & 0x0F)) )
                  {
                  EZ_reg.bits.RSRB.MCA = 1;
                  AddrDID = TRUE;
                  }
               //multicast mask address mode filter
               if( EZ_reg.bits.PFCRB.MCFEN && !EZ_reg.bits.PFCRB.ApnM && (((Data & 0x0F) & (EZ_reg.bytes.MCAMCM & 0x0F)) == ((EZ_reg.bytes.SFIDB & 0x0F) & (EZ_reg.bytes.MCAMCM & 0x0F))) )
                  {
                  EZ_reg.bits.RSRB.MCA = 1;
                  AddrDID = TRUE;
                  }
               //save the byte
               if( AddrDID || EZ_reg.bits.PFCRB.PREN)
                  EZ_reg.bytes.DIDB = Data & 0x0F;
               }
            //if the filter passed
            if( (AddrSID && AddrDID) || EZ_reg.bits.PFCRB.PREN )
               {//the received byte was correct
               //calc CRC
               Crc_On_Fly(Data);
               //set next state
               if( EZ_reg.bits.MCRB.DNPL )
                  {//dinamic packet length, go to receive the PL
                  EZInternalState = EZ_RxCheckPL;
                  return;
                  }
               else
                  {//fix packet length, go to receive the data
                  if( EZ_reg.bytes.RPLMPL < (PLEN_MAX + 1) )
                     {
                     DataByteCounter = 0;
                     Data1 = EZ_reg.bytes.RPLMPL;
                     EZInternalState = EZ_RxDataByte;
                     return;
                     }
                  }
               }
            }
         else
            {//normal address range network address mode
            if( EZ_reg.bits.MCRB.NWAD )
               AddrSID = TRUE;            //the state machine should receive the second byte of the network address to check it
            else
               {//not network address mode
               if( (EZ_reg.bits.PFCRB.SFEN && ((EZ_reg.bytes.SFLTNIDL & EZ_reg.bytes.SMSKNIDH) == (Data & EZ_reg.bytes.SMSKNIDH))) || !EZ_reg.bits.PFCRB.SFEN)
                  AddrSID = TRUE;
               }
            if( AddrSID || EZ_reg.bits.PFCRB.PREN )
               {//the data is correct
               //save the byte
               EZ_reg.bytes.SIDB = Data;
               //Calc CRC
               Crc_On_Fly(Data);
               //set next state
               EZInternalState = EZ_RxCheckDID;
               return;
               }
            }
         //address filter failure and inc. the error counter
         if( EZ_reg.bits.EDCRB.BADDR && (EZ_reg.bytes.EC[Frequency] < 255))
            EZ_reg.bytes.EC[Frequency]++;
         //go to the next freq or keep waiting for ACK
         if(EZ_state == EZMac_S_WaitingForAck)
			 EZMac_Ackwait(14);
		 else
			 Ch_Check_Start(TRUE);
         }
   break;

 /*Receiving the DID byte*/
   case EZ_RxCheckDID:
      if( It_Source == IT_SOURCE_T1 )
         //SW Watchdog timer overrun -> Trixie HW error
         _TrixieHWError();
      else
         {//DID received, read the data from the Trixie (Data)
         #ifdef SM_REAL_FUNCTION
          Data = _ReadByte_Trixie();
         #else
          Data = 0xF2;
         #endif
         AddrDID = FALSE;
         if( EZ_reg.bits.MCRB.NWAD )
            {//network address mode
            //broadcast filter
            if( EZ_reg.bits.PFCRB.BCEN && ((EZ_reg.bytes.SIDB == 0xFF) && (Data == 0xFF)) )
               {
               AddrDID = TRUE;
               EZ_reg.bits.RSRB.BCA = 1;
               }
            //DID filter
            if( !EZ_reg.bits.PFCRB.DFEN )
               AddrDID = TRUE;
            //network filter
            if( (EZ_reg.bytes.SIDB == EZ_reg.bytes.SFLTNIDL) && (Data == EZ_reg.bytes.SMSKNIDH) )
               AddrDID = TRUE;
            }
         else
            {//normal address mode
            //DID filter
            if( !EZ_reg.bits.PFCRB.DFEN )
               AddrDID = TRUE;
            //self address filter
            if( EZ_reg.bytes.SFIDB == Data )
               {
               AddrDID = TRUE;
               EZ_reg.bits.RSRB.SELFA = 1;
               }
            //broadcast filter
            if( EZ_reg.bits.PFCRB.BCEN && (Data == 0xFF) )
               {
               AddrDID = TRUE;
               EZ_reg.bits.RSRB.BCA = 1;
               }
            //multicast address mode filter
            if( EZ_reg.bits.PFCRB.MCFEN && EZ_reg.bits.PFCRB.ApnM && (EZ_reg.bytes.MCAMCM == Data) )
               {
               AddrDID = TRUE;
               EZ_reg.bits.RSRB.MCA = 1;
               }
            //multicast mask address mode filter
            if( EZ_reg.bits.PFCRB.MCFEN && !EZ_reg.bits.PFCRB.ApnM && ((Data & EZ_reg.bytes.MCAMCM) == (EZ_reg.bytes.SFIDB & EZ_reg.bytes.MCAMCM)) )
               {
               AddrDID = TRUE;
               EZ_reg.bits.RSRB.MCA = 1;
               }
            }
         //if the filtering passed
         if( AddrDID || EZ_reg.bits.PFCRB.PREN || EZ_reg.bits.PFWCRB.PFEN)
            {
			//Check if it is a forward only packet, or we need to signal it to the application
			if(AddrDID || EZ_reg.bits.PFCRB.PREN)
				ForwardOnly = 0; // No it is a valid packet
			else
				ForwardOnly = 1; // This is a forwardOnly packet
					
			//save the data
            EZ_reg.bytes.DIDB = Data;
            //calc CRC
            Crc_On_Fly(Data);
            //set next state
            if( EZ_reg.bits.MCRB.DNPL )
            {//dinamic packet length, go to receive the PL
               EZInternalState = EZ_RxCheckPL;
               return;
            }
            else
            {//fix packet length, go to receive the data
               if( EZ_reg.bytes.RPLMPL < (PLEN_MAX + 1) )
               {
                  DataByteCounter = 0;
                  Data1 = EZ_reg.bytes.RPLMPL;
                  EZInternalState = EZ_RxDataByte;
                  return;
               }
            }
         }
	  }
      //addres filter failure, inc. the error counter
      if( EZ_reg.bits.EDCRB.BADDR && (EZ_reg.bytes.EC[Frequency] < 255))
         EZ_reg.bytes.EC[Frequency]++;
      //go to the next freq.
	  if(EZ_state == EZMac_S_WaitingForAck)
	  	EZMac_Ackwait(16);
	  else
	    Ch_Check_Start(TRUE);
   break;

 /*Receiving the PL byte*/
   case EZ_RxCheckPL:
      if( It_Source == IT_SOURCE_T1 )
         //SW Watchdog timer overrun -> Trixie HW error
         _TrixieHWError();
      else
         {//PL received, read the data from the Trixie (Data)
         #ifdef SM_REAL_FUNCTION
          Data = _ReadByte_Trixie();
         #else
          Data = 0x03;
         #endif
         AddrSID = FALSE;
         //packet length filter
         if( !EZ_reg.bits.PFCRB.PLFEN )
            AddrSID = TRUE;
         //dinamic packet length, max value filter
         if( EZ_reg.bits.MCRB.DNPL && (Data < EZ_reg.bytes.RPLMPL + 1) )
            AddrSID = TRUE;
         if( EZ_reg.bits.PFCRB.PREN )
            AddrSID = TRUE;
         //PLEN_MAX filter
         if( (Data > PLEN_MAX) || (Data == 0) )
            AddrSID = FALSE;
         //all filter passed
         if( AddrSID )