📄 iai_ezmac_lite_int.c
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if (Data) //cycle counter, check CRL until {Packet_Start_Timeout="number of preambles+3" (2D D4 and the first data byte)} ms
{ // in every ms
Data--;
SEL_PIN = 0;
Spi_Comm0();
CLK_PIN = 1; //go to the CRL bit (previously we were at DQD bit in the status)
CLK_PIN = 0;
if (MISO_PIN) //Test Clock Recovery locked bit
{
_Set_Timer1( 65535 - (CRL_CHECK_TIMER_LIMIT) ); //next round
SEL_PIN = 1;
break;
}
}
//No clock recovery, we are receiving an FSK signal which is not sent for us, or the Packet_Start_Timeout ended. -> go away!
SEL_PIN = 1;
//go to the next channel
Ch_Check_Start(TRUE);
}
else
{//CID is in the FIFO
//set the Soft WDTimer for RX
#ifdef SM_SOFTWDT_EN
//enable the software watchdog timer for receiving
_Set_Timer1(MAX_RX_PACKET_TIMER);
#endif
//read the data from the Trixie (Data)
#ifdef SM_REAL_FUNCTION
Data = _ReadByte_Trixie();
#else
Data = 0xCD; //only for test
#endif
#ifdef SM_PRINTF
printf("%x\n\r",Data);
#endif
//check the CID
if( ((EZ_reg.bits.PFCRB.CFEN && (Data == EZ_reg.bytes.CIDB)) || (!EZ_reg.bits.PFCRB.CFEN)) || EZ_reg.bits.PFCRB.PREN )
{
//save the byte
EZ_reg.bytes.RX_CIDB = Data;
EZInternalState = EZ_RxCheckSID;
//Calc CRC
Crc_On_Fly(Data);
}
else
{
//go to the next freq.
Ch_Check_Start(TRUE);
}
}
break;
/*receiving the first or second byte*/
case EZ_RxCheckSID:
#ifdef SM_TRIGGER_SID
TRIGGER = 1; //trigger output for oscilloscope
#endif
#ifdef SM_PRINTF
printf("ChSID: ");
#endif
#ifdef SM_PRINT_STATE
_PrintState();
#endif
if( It_Source == IT_SOURCE_T1 )
{ //SW Watchdog timer overrun
_TrixieHWError();
}
else
{ //SID received, read the data from the Trixie (Data)
#ifdef SM_REAL_FUNCTION
Data = _ReadByte_Trixie();
#else
Data = 0xF1;
#endif
#ifdef SM_PRINTF
printf("%x\n\r",Data);
#endif
//check the SID
AddrSID = FALSE;
AddrDID = FALSE;
//normal address mode
if( (EZ_reg.bits.PFCRB.SFEN && ((EZ_reg.bytes.SFLTB & EZ_reg.bytes.SMSKB) == (Data & EZ_reg.bytes.SMSKB))) || !EZ_reg.bits.PFCRB.SFEN)
AddrSID = TRUE;
if( AddrSID || EZ_reg.bits.PFCRB.PREN )
{ //the data is correct
//save the byte
EZ_reg.bytes.SIDB = Data;
//Calc CRC
Crc_On_Fly(Data);
//set next state
EZInternalState = EZ_RxCheckDID;
return;
}
//address filter failure
Ch_Check_Start(TRUE); //go to the next freq.
}
break;
/*Receiving the DID byte*/
case EZ_RxCheckDID:
#ifdef SM_PRINTF
printf("ChDID: ");
#endif
#ifdef SM_PRINT_STATE
_PrintState();
#endif
if( It_Source == IT_SOURCE_T1 ) //SW Watchdog timer overrun -> Trixie HW error
_TrixieHWError();
else
{ //DID received, read the data from the Trixie (Data)
#ifdef SM_REAL_FUNCTION
Data = _ReadByte_Trixie();
#else
Data = 0xF2;
#endif
#ifdef SM_PRINTF
printf("%x\n\r",Data);
#endif
AddrDID = FALSE;
//DID filter
if( !EZ_reg.bits.PFCRB.DFEN )
AddrDID = TRUE;
//self address filter
if( EZ_reg.bytes.SFIDB == Data )
{
AddrDID = TRUE;
EZ_reg.bits.RSRB.SELFA = 1;
}
//broadcast filter
if( EZ_reg.bits.PFCRB.BCEN && (Data == 0xFF) )
{
AddrDID = TRUE;
EZ_reg.bits.RSRB.BCA = 1;
}
//if the filtering passed
if( AddrDID || EZ_reg.bits.PFCRB.PREN)
{
//save the data
EZ_reg.bytes.DIDB = Data;
//calc CRC
Crc_On_Fly(Data);
//set next state
if( EZ_reg.bytes.RPLB < (PLEN_MAX + 1) )
{
DataByteCounter = 0;
/*changed by krk for rev1.3 -> during rx the PLENB register will be not changed if fixed packet length is activated!*/
//EZ_reg.bytes.PLENB = EZ_reg.bytes.RPLMPL;
Data1 = EZ_reg.bytes.RPLB;
EZInternalState = EZ_RxDataByte;
return;
}
}
}
//addres filter failure, go to the next freq.
Ch_Check_Start(TRUE);
break;
/*Receiving the Data bytes*/
case EZ_RxDataByte:
{
#ifdef SM_PRINTF
printf("RxD: ");
#endif
#ifdef SM_PRINT_STATE
_PrintState();
#endif
if( It_Source == IT_SOURCE_T1 )
//SW Watchdog timer overrun -> Trixie HW error
_TrixieHWError();
else
{//Data byte received, read the data from the Trixie (Data)
#ifdef SM_REAL_FUNCTION
Data = _ReadByte_Trixie();
#else
Data = DataByteCounter;
#endif
#ifdef SM_PRINTF
printf("%x\n\r",Data);
#endif
//save Data
EZ_reg.bytes.DBuff[DataByteCounter] = Data;
//calc CRC
Crc_On_Fly(Data);
DataByteCounter++;
//it was the last byte?
/*changed by krk for rev1.3 -> during rx the PLENB register will be not changed if fixed packet length is activated!*/
/*extra safety for rev1.5 by krk*/
if( (DataByteCounter == Data1) || (DataByteCounter == PLEN_MAX) )//EZ_reg.bytes.PLENB )
EZInternalState = EZ_RxCheckEDC;
}
break;
}
/*Receiving the EDC bytes*/
case EZ_RxCheckEDC:
{
#ifdef SM_PRINTF
printf("ChEDC: ");
#endif
#ifdef SM_PRINT_STATE
_PrintState();
#endif
if( It_Source == IT_SOURCE_T1 ) //SW Watchdog timer overrun -> Trixie HW error
_TrixieHWError();
else
{ //EDC byte received, read the data from the Trixie (Data)
#ifdef SM_REAL_FUNCTION
Data = _ReadByte_Trixie();
#else
if( (DataByteCounter == (Data1 + 1)) || (DataByteCounter == PLEN_MAX + 1) ))
//second CRC
Data = 0x50;
else
//first CRC
Data = 0x29;
#endif
#ifdef SM_PRINTF
printf("%x\n\r",Data);
#endif
//Calc the CRC for the received CRC
Crc_On_Fly(Data);
DataByteCounter++;
if(DataByteCounter == (Data1 + 2) || (DataByteCounter == PLEN_MAX + 2) ) //Is the second CRC byte arrived?
{
//Is the CRC correct?
if(EZ_crc.adat == 0)
{
//turn off Trixie after correct Rx
#ifdef ARSSI_USED
ARSSI_value=(read_adc( ADC_READ_ONLY ));
//switch off ADC, save current
setup_adc( ADC_OFF );
#else
ARSSI_value = 0x23;
#endif
#ifdef SM_REAL_FUNCTION
EZ_commands.arr[Fifo_command] &=0xFFFD; //reset synchron latch
EZRadio_CMD_Write(Fifo_command);
EZ_commands.arr[Config_command]=0x8000 | FREQ_Band | XTAL_COMP; //switch off TX latch, and RX FIFO
EZRadio_CMD_Write(Config_command);
EZ_commands.arr[Power_command] &= 0xff0f; //switch off receiver
EZRadio_CMD_Write(Power_command);
EZRadio_Statusread (); //reset all non latched IT in Trixie
EZ_reg.bits.RSRB.PRF = Frequency & 0x07;
EZ_state = EZMac_S_PacketValid;
#endif
EZInternalState = EZ_RxEnd;
_Turn_Off_Timer1();
disable_interrupts( INT_EXT );
//next states will not read data bytes -> External Interrupt routine should set the SPI select pin
SetSpiEn = TRUE;
}
else
{//CRC error
//go to the next freq
Ch_Check_Start(TRUE);
}
}
else
{//first CRC byte
//read out the DRSSI value from the Trixie (EZ_reg.bits.RSRB.DRSSI)
#ifdef SM_REAL_FUNCTION
EZ_reg.bits.RSRB.DRSSI = _DRSSI_Read();
#endif
if(EZ_reg.bits.MCRB.ADEN)
{//start AD conversion to measure the ARSSI value
/*changed by krk for rev 1.51 -> measure the ARSSI, start (only) the ADC*/
#ifdef ARSSI_USED
read_adc(ADC_START_ONLY);
#endif
}
}
}
break;
}
/*End of the receiving*/
case EZ_RxEnd:
#ifdef SM_PRINTF
printf("RxE\n\r");
#endif
#ifdef SM_PRINT_STATE
_PrintState();
#endif
break;
/*Transmit error state*/
case EZ_TransmitError:
#ifdef SM_PRINT_STATE
_PrintState();
#endif
#ifdef SM_PRINTF_TX
printf("TxE\n\r");
#endif
break;
/*Channel check before transmit*/
case EZ_TxCheckChannel:
{
#ifdef SM_TRIGGER_TX
TRIGGER = 1;
#endif
#ifdef SM_PRINT_STATE
_PrintState();
#endif
#ifdef SM_PRINTF_TX
printf("TxChC\n\r");
#endif
if( It_Source != IT_SOURCE_T1 )
{//HW error, not T1 IT
_TrixieHWError();
return;
}
//DQD check
if( Data1 == 0 ) //this is the first DQD check round
{
//multiplex the DQD to the MISO pin
SEL_PIN = 0;
Spi_Comm0();
}
//save DQD value: only the last logic high value of the DQD will increment the counter
if( _DQD_Check() )
Data++;
else
Data = 0;
//increment the sample counter
Data1++;
if(Data1 == DQD_SAMPLE)
{ //after sampling we should check the result
SEL_PIN = 1; //set the select pin
#ifdef SM_REAL_FUNCTION
EZ_commands.arr[Power_command] &= 0xff0f; //switch off receiver
EZRadio_CMD_Write(Power_command);
#endif
//is the DQD 1 or 0?
if( Data > 2)
{//channel occupied
//go to the TxError state
_GotoTxErrorState();
return;
}
else
{//the channel is IDLE, the packet can be sent
// Configure Trixie to start TX
#ifdef SM_REAL_FUNCTION
EZ_commands.arr[Config_command]=0x8000 | FREQ_Band | XTAL_COMP | TXREG_USED; //switch on TX reg.
EZRadio_CMD_Write(Config_command);
EZ_commands.arr[Power_command] |= 0x0020; //switch on the transmitter
EZRadio_CMD_Write(Power_command);
#endif
#ifdef SM_TRIGGER_TX
TRIGGER = 1;
#endif
//set next state
EZ_state = EZMac_S_TxPacket;
EZInternalState = EZ_TxSendPreamble;
//setup SW Watchdog timer
#ifdef SM_SOFTWDT_EN
_Set_Timer1(MAX_TX_PACKET_TIMER);
#endif
//enable ext IT
clear_interrupt( INT_EXT );
enable_interrupts( INT_EXT );
}
}
else
{
//next sample Start Timer1
_Set_Timer1(DQD_TIMER_LIMIT);
}
break;
}
/*Send preamble bytes*/
case EZ_TxSendPreamble:
{
#ifdef SM_PRINT_STATE
_PrintState();
#endif
if (It_Source == IT_SOURCE_T1)
{ //SW Watchdog timer overrun -> Trixie HW error
_TrixieHWError();
return;
}
//write byte (0xAA) to the Trixie
#ifdef SM_REAL_FUNCTION
_WriteByte_Trixie (0xAA);
#endif
AddrSID = TRUE;
#ifdef SM_PRINTF_TX
printf("TxPre: AA\n\r");
#endif
if(DataByteCounter == 0)
EZInternalState = EZ_TxSendSyncPattern0;
else
DataByteCounter--;
break;
}
/*Send the first sync pattern: 2D, calc the CRC for the first header byte*/
case EZ_TxSendSyncPattern0:
{
#ifdef SM_PRINT_STATE
_PrintState();
#endif
if( It_Source == IT_SOURCE_T1 )
{//SW Watchdog timer overrun -> Trixie HW error
_TrixieHWError();
return;
}
//write byte (0x2D) to the Trixie
#ifdef SM_REAL_FUNCTION
_WriteByte_Trixie (0x2d);
#endif
DataByteCounter = 0;
//CID is used, this is the first byte of the header
Data = EZ_reg.bytes.CIDB;
//calc CRC for this byte
Crc_On_Fly(Data);
//go to the next state
EZInternalState = EZ_TxSendSyncPattern1;
#ifdef SM_PRINTF_TX
printf("TxSy0: 2D %x\n\r",Data);
#endif
break;
}
/*Send the second sync pattern byte: D4, calc the CRC for the 2nd header byte*/
case EZ_TxSendSyncPattern1:
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