📄 iai_ezmac_lite_int.c
字号:
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\
* *
* FILE NAME: IAI_EZMac_Lite_Int.c *
* *
* DESIGNER: Lukacs, Miklos; Kovacs, Krisztian *
* PROGRAMMER: Lukacs, Miklos *
* *
* DESCRIPTION: EZMac internal functions *
* *
* REVISION: 01_5 Maj 10, 2005 From the original EZmac version *
* removed: *
* - Multicast addressing. *
* - Network address mode. *
* - Reduced address mode. *
* - Dynamic packet length. *
* - Error detection. *
* - CID is mandatory. *
* 01_6 Aug 11, 2005 FIFO restart after HW error, *
* Timer IT handling improvements *
* 01_7 Dec 08, 2005 Port to HiTech *
* *
\* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
#define SM_REAL_FUNCTION
#ifdef SM_REAL_FUNCTION
#define SM_SOFTWDT_EN //turn on the software watchdog timers
#ifndef END_HARDWARE
// #define SM_PRINT_STATE //debug functions!
#define SM_DEBUG
#endif
#else
#ifndef END_HARDWARE
#define SM_DEBUG
#define SM_PRINT_STATE
// #define SM_PRINTF
// #define SM_PRINTF_TX
#endif
#endif
#ifdef SM_DEBUG
#define SM_TRIGGER_DQD
// #define SM_TRIGGER_CID
// #define SM_TRIGGER_SID
#define SM_TRIGGER_TX
#endif
//===============================================================================================
#pragma separate
void Ch_Check_Start (bool ChangeFreq)
{
// Changed by Laszlo Kadar on 29.11.05
#ifdef HITECH_COMPILER
static _NEAR__ bool BANK_2 NextFreq;
static _NEAR__ int BANK_2 Reg;
#endif
#ifdef CCS_C_COMPILER
bool NextFreq;
int Reg;
#endif
#ifdef FIX_MEM_ADDRESS
#pragma byte ChangeFreq = 0x63
#pragma bit NextFreq = 0x64.0
#pragma byte Reg = 0x65
#endif
#ifdef SM_DEBUG
TRIGGER = 0;
#endif
//turn of FIFO of Trixie
//next states will not read data bytes -> External Interrupt routine should set the SPI select pin
SetSpiEn = TRUE;
#ifdef SM_REAL_FUNCTION
EZ_commands.arr[Fifo_command] &=0xFFFD; //reset synchron latch
EZRadio_CMD_Write(Fifo_command);
#endif
disable_interrupts( INT_EXT );
//set the frequency
if( ChangeFreq && EZ_reg.bits.RCRB.SCHEN )
{
Reg = (0xFF >> (7 - EZ_reg.bits.MCRB.NRF));
//are all of the available frequencys masked?
if( (EZ_reg.bytes.FMASKB & Reg) == Reg )
//all of the freq are masked -> failure; the state machine stay in the current frequency
NextFreq = FALSE;
else
NextFreq = TRUE;
while(NextFreq)
{
if( Frequency < EZ_reg.bits.MCRB.NRF )
{//it isn't the last frequency
Frequency++;
if( ((EZ_reg.bytes.FMASKB >> Frequency) & 0x01) == 0 )
//this frequency isn't masked -> end of search
NextFreq = FALSE;
}
else
{//go to the first frequency
Frequency = 0;
if( ((EZ_reg.bytes.FMASKB >> Frequency) & 0x01) == 0 )
//this frequency isn't masked -> end of search
NextFreq = FALSE;
}
}
}
//if the search of the channel isn't active, set the default frequency
if( !EZ_reg.bits.RCRB.SCHEN )
Frequency = (int8)EZ_reg.bits.RCRB.RF;
//configure Trixie for new freq (Frequency)
#ifdef SM_REAL_FUNCTION
EZ_commands.arr[Freq_command]=0xA000 + ((int16)(EZ_reg.bytes.FR[Frequency]-1)*FREQ_step+FREQ_start);
EZRadio_CMD_Write(Freq_command);
#endif
#ifdef SM_PRINTF
printf("F: %x\n\r",Frequency);
#endif
//set the RSR register to the default value
EZ_reg.bytes.RSRB = 0;
//Set the next state
// Changed by Laszlo Kadar on 26.11.05
EZ_state = EZMac_S_RxDQDCheck;
EZInternalState = EZ_RxDQDCheck;
//set the DQD Check init values
Data = 0;
Data1 = 0;
//Start T1 to first DQD check
_Set_Timer1(FIRST_DQD_TIMER_LIMIT);
}
//===============================================================================================
#pragma separate
bool _DQD_Check (void)
{
#ifdef SM_REAL_FUNCTION
if( MISO_PIN )
return 1;
else
return 0;
#else
return TRUE; //only for debug
#endif
}
//===============================================================================================
#pragma separate
bool _DRSSI_Read (void)
{
//Read the DRSSI from the Trixie
SEL_PIN = 0;
STRH=Spi_Comm0();
SEL_PIN = 1;
return (STRH & DRSSI_bit);
}
//===============================================================================================
#pragma separate
void _GotoTxErrorState(void)
{
#ifdef SM_REAL_FUNCTION
EZ_commands.arr[Power_command] &= 0xff0f; //switch off Trixie
EZRadio_CMD_Write(Power_command);
#endif
//Set the next state
EZ_state = EZMac_S_TxError;
EZInternalState = EZ_TransmitError;
//disable all IT
_Turn_Off_Timer1();
disable_interrupts( INT_EXT );
}
//===============================================================================================
#pragma separate
void _TrixieHWError(void)
{
#ifdef SM_REAL_FUNCTION
#ifdef SM_DEBUG
TRIGGER = 0;
#endif
//restart Trixie
disable_interrupts( INT_EXT );
EZ_commands.arr[Config_command]=0x8000 | FREQ_Band | XTAL_COMP;
EZ_commands.arr[Fifo_command]=FIFO_cmd_init_value; //Fill:synchron pattern; IT level:8; disable sensitive reset
EZ_commands.arr[Data_Rate_command]=DR_cmd_init_value; //8842bps
EZ_commands.arr[RX_Ctrl_command]=RX_cmd_init_value; // BW:135kHz; VDI:always on; LNA:max; DRSSI:-103; Pin8: VDIout
EZ_commands.arr[RX_Ctrl_command] &= 0xFFF8;
EZ_commands.arr[RX_Ctrl_command] |= (int16)((EZ_reg.bytes.RCRB & 0x70) >> 4);
EZ_commands.arr[TX_Ctrl_command]=TX_cmd_init_value & 0xfff1; //f0+df; df:75kHz; Pout:-3dB!!!!
EZ_commands.arr[TX_Ctrl_command] &= 0xFFF8;
EZ_commands.arr[TX_Ctrl_command] |= (int16)((EZ_reg.bytes.TCRB & 0x38) >> 3);
EZ_commands.arr[Data_Filter_command]=DF_cmd_init_value; //CR:slow; Digital LPF; DQD:7
EZ_commands.arr[AFC_command]=AFC_cmd_init_value; //enabled; fine mode; auto,keep offset; +7/-8; output enabled
EZRadio_CMD_Write(Config_command);
EZRadio_CMD_Write(Fifo_command);
EZRadio_CMD_Write(Data_Rate_command);
EZRadio_CMD_Write(TX_Ctrl_command);
EZRadio_CMD_Write(RX_Ctrl_command);
EZRadio_CMD_Write(Data_Filter_command);
EZRadio_CMD_Write(AFC_command);
EZRadio_Statusread (); //read all IT status bit
#endif
//next states will not read data bytes -> External Interrupt routine should set the SPI select pin
SetSpiEn = TRUE;
//In which state did the failure occured?
if( EZInternalState > EZ_RxEnd )
{//during tx -> goto TxError state
_GotoTxErrorState();
return;
}
if ( (EZInternalState < EZ_TxCheckChannel) && (EZInternalState > EZ_WakeUp) )
/*changed by mlu for rev1.6 -> after HW error the Rx FIFO wasn't switched on*/
{//during rx
//switch on Rx and FIFO
EZ_commands.arr[Config_command]=0x8000 | FREQ_Band | XTAL_COMP | FIFO_USED; //switch on RX FIFO
EZRadio_Write(EZ_commands.arr[Config_command]);
EZRadio_Statusread ();
//goto new freq
Ch_Check_Start(TRUE);
return;
}
//if else, then stay in the current state
}
//===============================================================================================
#pragma separate
int8 _ReadByte_Trixie(void)
{
// Changed by Laszlo Kadar on 29.11.05
#ifdef HITECH_COMPILER
static _NEAR__ int8 BANK_2 data;
#endif
#ifdef CCS_C_COMPILER
int8 data;
#endif
data=Spi_Comm0();
SEL_PIN = 1;
return data;
}
//===============================================================================================
#pragma separate
void _WriteByte_Trixie (int8 data)
{
SEL_PIN = 0; //SEL=0
EZ_Spi_Write(0x0B8);
EZ_Spi_Write(data);
SEL_PIN = 1; //SEL=1
}
//===============================================================================================
#ifdef SM_PRINT_STATE
#pragma separate
/*only for debug: put the nukber of the state to the IO ports*/
void _PrintState(void)
{
// Changed by Laszlo Kadar on 29.11.05
#ifdef HITECH_COMPILER
_NEAR__ int8 BANK_2 temp;
#endif
#ifdef CCS_C_COMPILER
int8 temp;
#endif
temp = portc_reg.adat;
temp &= 0xF0;
temp |= ((EZInternalState & 0x0F));
portc_reg.adat = temp;
}
#endif
//===============================================================================================
#pragma separate
void State_Machine (char It_Source)
{
// Changed by Laszlo Kadar on 29.11.05
#ifdef HITECH_COMPILER
static _NEAR__ bool BANK_2 AddrSID, AddrDID, FirstError;
static _NEAR__ int16 BANK_2 TimerSet;
#endif
#ifdef CCS_C_COMPILER
bool AddrSID, AddrDID, FirstError;
int16 TimerSet;
#endif
#ifdef FIX_MEM_ADDRESS
#pragma byte It_Source = 0x67
#pragma bit AddrSID = 0x64.1
#pragma bit AddrDID = 0x64.2
#pragma bit FirstError = 0x64.3
#endif
#ifdef SM_DEBUG
LED4 = 1; //trigger output to measure the State Machine timing
#endif
if( (It_Source == IT_SOURCE_OVUR) || (It_Source == IT_SOURCE_COMM_OVUR) )
{//Trixie HW error: overrun or underrun!
_TrixieHWError();
return;
}
switch( EZInternalState )
{
/*Idle state*/
case EZ_Idle:
#ifdef SM_PRINTF
printf("Idle\n\r");
#endif
#ifdef SM_PRINT_STATE
_PrintState();
#endif
break;
/*Sleep state*/
case EZ_Sleep:
#ifdef SM_PRINTF
printf("Sleep\n\r");
#endif
#ifdef SM_PRINT_STATE
_PrintState();
#endif
break;
/*after waking up*/
case EZ_WakeUp:
if ( It_Source != IT_SOURCE_T1 )
{
//waking up error
#ifdef SM_PRINTF
printf("W E\n\r");
#endif
_TrixieHWError();
_Turn_Off_Timer1();
}
//changed by mlu for rev1.4
EZ_commands.arr[Wake_command]=WK_cmd_init_value; // very long...
EZRadio_CMD_Write(Wake_command);
EZ_commands.arr[Power_command] |= 0x0002; //switch on the wake-up timer
EZRadio_CMD_Write(Power_command);
//set next state
EZ_state = EZMac_S_Idle;
EZInternalState = EZ_Idle;
#ifdef SM_PRINTF
printf("WakeUp\n\r");
#endif
#ifdef SM_PRINT_STATE
_PrintState();
#endif
break;
/*channel check before receiving*/
case EZ_RxDQDCheck:
#ifdef SM_PRINTF
printf("DQDCh\n\r");
#endif
#ifdef SM_PRINT_STATE
_PrintState();
#endif
if( Data1 == 0 )
{//it will be the first DQD
//multiplex the DQD bit to the MISO pin
SEL_PIN = 0;
Spi_Comm0();
}
//is the DQD 1 or 0?
//save DQD value: only the last logic high value of the DQD will increment the counter
if( _DQD_Check() )
Data++;
else
Data = 0;
//increment the number of the sample counter
Data1++;
if(Data1 == DQD_SAMPLE)
{//after sampling we should check the result
//set the select pin
SEL_PIN = 1;
if( Data > 2)
{//at least the last 3 DQD was logic high
//we can receive any data; wait for IRQ -> after TIMER1 IT and the DQD is OK, or after EXT IT (the sync pattern is received)
//Turn on the FIFO of Trixie
#ifdef SM_REAL_FUNCTION
EZ_commands.arr[Fifo_command] |= 0x0002; //enable synchron latch
EZRadio_CMD_Write(Fifo_command);
#endif
clear_interrupt( INT_EXT );
enable_interrupts( INT_EXT );
//init CRC calculation routine
Crc_Init();
Data = EZ_reg.bits.MCRB.NRF + 7; //this will be the cycle counter of the CRL checking in the next state
//number of preamble + 3 (2D D4 and the first data byte)
_Set_Timer1( 65535 - (ONE_BYTE_TIMER_LIMIT) ); //we will check the CRL bit 2.5ms later than we switched
//next states will read data byte from the FIFO, the External Interrupt routine shouldn't set the SPI select pin!
SetSpiEn = FALSE;
//Set next state
EZInternalState = EZ_RxCheckCID;
EZ_state = EZMac_S_Receiving;
FirstError = TRUE;
}
else
{//DQD was logic low more than twice -> no valid FSK data
Ch_Check_Start(TRUE);
}
//set the init values /*deleted by krk*/
//Data = 0;
//Data1 = 0;
}
else
{
//Start Timer1 -> read next sample of DQD
_Set_Timer1(DQD_TIMER_LIMIT);
}
break;
/*receiving the first byte*/
case EZ_RxCheckCID:
#ifdef SM_TRIGGER_CID
TRIGGER = 1;
#endif
#ifdef SM_PRINTF
printf("ChCID: ");
#endif
#ifdef SM_PRINT_STATE
_PrintState();
#endif
if( It_Source == IT_SOURCE_T1 )
{ //Timer IRQ -> CRL checking
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -