iai_ezmac_pic.c

Integration的EZMac Lite

 #pragma byte rcsta = 0x18
 #pragma byte rcreg = 0x1A
 #pragma bit oerr = rcsta.1
 #pragma bit ferr = rcsta.2
 #pragma bit cren = rcsta.4

 #pragma use standard_io(A)
 #pragma use standard_io(B)
 #ifdef END_HARDWARE
  #pragma use standard_io(C)
 #endif
#endif

#ifdef HITECH_COMPILER
 static volatile unsigned char rcsta @ 0x18;
 static volatile unsigned char rcreg @ 0x1A;
 static volatile bit oerr @ (unsigned)&rcsta*8+1;
 static volatile bit ferr @ (unsigned)&rcsta*8+2;
 static volatile bit cren @ (unsigned)&rcsta*8+4;
#endif

/**************************************************************************\
   		     			        Include files   			  
\**************************************************************************/
#ifdef CCS_C_COMPILER
// #include "IAI_EZMac_PIC.h"
 #include "IAI_EZMac_Lite.h"
 #include "IAI_EZMac_Lite_Int.h"
 #include <string.h>
 #include "IAI_EZMac_Lite_Int.c"
 #include "IAI_EZMac_Lite.c"
#endif

#ifdef HITECH_COMPILER
// #include "IAI_EZMac_PIC.h"
 #include "IAI_EZMac_Lite.h"
 #include "IAI_EZMac_Lite_Int.h"
 #include <string.h>
 #include <stdio.h>
 #include "IAI_EZMac_Lite_Int.c"
 #include "IAI_EZMac_Lite.c"
#endif


/**************************************************************************\
   			        Declare interrupt functions			  
\**************************************************************************/
#ifdef CCS_C_COMPILER
 #pragma priority rtcc, rda
#endif
#ifdef HITECH_COMPILER
#endif

#ifdef CCS_C_COMPILER
 // External interrupt routine
 #pragma int_ext
 void Ext_ISR (void)
 {
    EZMac_CommISR ();
 }
 // peripheral interrupt routines
 #pragma int_timer1
 void TimerISR (void)
 {
    EZMac_TimerISR ();
 }
#endif

#ifdef HITECH_COMPILER
 void Ext_ISR (void)
 {
    EZMac_CommISR ();
 }
// #pragma inline(Ext_ISR)

 void TimerISR (void)
 {
    EZMac_TimerISR ();
 }
// #pragma inline(TimerISR)

 #define INT_EXT_ISR Ext_ISR
 #define INT_TIMER1_ISR TimerISR

/*
 #ifdef END_HARDWARE
  void MAIN_hardint(void);
  #define INT_TIMER0_ISR MAIN_hardint
 #else
  void MAIN_hardint(void);
  #define INT_TIMER2_ISR MAIN_hardint
 #endif                                //#ifdef END_HARDWARE
*/

 #define INT_RDA_ISR RC_FIFO_int
 #define INT_TBE_ISR TX_int

 #pragma interrupt_level 1
 void interrupt ISR(void)
 {
 #ifdef INT_RDA_ISR
  if(RCIE==1 && RCIF==1)
  {
    RCIF=0;
    INT_RDA_ISR();
  }
 #else
  if(RCIE==1 && RCIF==1)
  {
    RCIF=0;
  }
 #endif
 #ifdef INT_TIMER0_ISR
  if(TMR0IE==1 && TMR0IF==1)
  {
   TMR0IF=0;
   INT_TIMER0_ISR();
  }
 #else
  if(TMR0IE==1 && TMR0IF==1)
  {
   TMR0IF=0;
  }
 #endif
 #ifdef INT_RTCC_ISR
  if(TMR0IE==1 && TMR0IF==1)
  {
   TMR0IF=0;
   INT_RTCC_ISR();
  }
 #else
  if(TMR0IE==1 && TMR0IF==1)
  {
   TMR0IF=0;
  }
 #endif
#ifdef END_HARDWARE
 #ifdef INT_EXT_ISR
  if(INT0IE==1 && INT0IF==1)
  {
    INT0IF=0;
    INT_EXT_ISR();
  }
 #else
  if(INT0IE==1 && INT0IF==1)
  {
    INT0IF=0;
  }
 #endif
#else
 #ifdef INT_EXT_ISR
  if(INTE==1 && INTF==1)
  {
    INTF=0;
    INT_EXT_ISR();
  }
 #else
  if(INTE==1 && INTF==1)
  {
    INTF=0;
  }
 #endif
#endif
 #ifdef INT_RB_ISR
  if(RBIE==1 && RBIF==1)
  {
    RBIF=0;
    INT_RB_ISR();
  }
 #else
  if(RBIE==1 && RBIF==1)
  {
    RBIF=0;
  }
 #endif
 #ifdef __PINS_40
  #ifdef INT_PSP_ISR
   if(PSPIE==1 && PSPIF==1)
   {
     PSPIF=0;
     INT_PSP_ISR();
   }
  #else
   if(PSPIE==1 && PSPIF==1)
   {
     PSPIF=0;
   }
  #endif
 #endif
 #ifdef INT_AD_ISR
  if(ADIE==1 && ADIF==1)
  {
    ADIF=0;
    INT_AD_ISR();
  }
 #else
  if(ADIE==1 && ADIF==1)
  {
    ADIF=0;
  }
 #endif
 #ifdef INT_SSP_ISR
  if(SSPIE==1 && SSPIF==1)
  {
    SSPIF=0;
    INT_SSP_ISR();
  }
 #else
  if(SSPIE==1 && SSPIF==1)
  {
    SSPIF=0;
  }
 #endif
 #ifdef INT_CCP1_ISR
  if(CCP1IE==1 && CCP1IF==1)
  {
    CCP1IF=0;
    INT_CCP1_ISR();
  }
 #else
  if(CCP1IE==1 && CCP1IF==1)
  {
    CCP1IF=0;
  }
 #endif
 #ifdef INT_TIMER2_ISR
  if(TMR2IE==1 && TMR2IF==1)
  {
   TMR2IF=0;
   INT_TIMER2_ISR();
  }
 #else
  if(TMR2IE==1 && TMR2IF==1)
  {
   TMR2IF=0;
  }
 #endif
 #ifdef INT_TIMER1_ISR
  if(TMR1IE==1 && TMR1IF==1)
  {
   TMR1IF=0;
   INT_TIMER1_ISR();
  }
 #else
  if(TMR1IE==1 && TMR1IF==1)
  {
   TMR1IF=0;
  }
 #endif
 #ifdef INT_EEPROM_ISR
  if(EEIE==1 && EEIF==1)
  {
   EEIF=0;
   INT_EEPROM_ISR();
  }
 #else
  if(EEIE==1 && EEIF==1)
  {
   EEIF=0;
  }
 #endif
 #ifdef INT_BUSCOL_ISR
  if(BCLIE==1 && BCLIF==1)
  {
   BCLIF=0;
   INT_BLC_ISR();
  }
 #else
  if(BCLIE==1 && BCLIF==1)
  {
   BCLIF=0;
  }
 #endif
 #ifdef INT_CCP2_ISR
  if(CCP2IE==1 && CCP2IF==1)
  {
   CCP2IF=0;
   INT_CCP2_ISR();
  }
 #else
  if(CCP2IE==1 && CCP2IF==1)
  {
   CCP2IF=0;
  }
 #endif
 #ifdef INT_TBE_ISR
  if(TXIE==1 && TXIF==1)
  {
    TXIF=0;
    INT_TBE_ISR();
  }
 #else
  if(TXIE==1 && TXIF==1)
  {
    TXIF=0;
  }
 #endif
 }
#endif

/**************************************************************************\
   			          SPI port handling
\**************************************************************************/
#ifdef SW_SPI
 /*software SPI is used (bit bang mode)*/
 //Changed by Laszlo Kadar on 29.11.05
#ifdef HITECH_COMPILER
 static _NEAR__ reg_union BANK_2 u_reg;
#endif
#ifdef CCS_C_COMPILER
 static reg_union u_reg;
#endif
 #ifdef FIX_MEM_ADDRESS
  #ifdef CCS_C_COMPILER
   #pragma locate u_reg=0x62
  #endif
 #endif
 int8 Spi_Comm0(void)
 {
   MOSI_PIN = 0;
   CLK_PIN = 0;

   CLK_PIN = 1;
   u_reg.testreg.bit7 = MISO_PIN;
   CLK_PIN = 0;

   CLK_PIN = 1;
   u_reg.testreg.bit6 = MISO_PIN;
   CLK_PIN = 0;

   CLK_PIN = 1;
   u_reg.testreg.bit5 = MISO_PIN;
   CLK_PIN = 0;

   CLK_PIN = 1;
   u_reg.testreg.bit4 = MISO_PIN;
   CLK_PIN = 0;

   CLK_PIN = 1;
   u_reg.testreg.bit3 = MISO_PIN;
   CLK_PIN = 0;

   CLK_PIN = 1;
   u_reg.testreg.bit2 = MISO_PIN;
   CLK_PIN = 0;

   CLK_PIN = 1;
   u_reg.testreg.bit1 = MISO_PIN;
   CLK_PIN = 0;

   CLK_PIN = 1;
   u_reg.testreg.bit0 = MISO_PIN;
   CLK_PIN = 0;

  return u_reg.adat;
 }

 //===============================================================================================

// Changed by Laszlo Kadar on 26.11.05
#ifdef HITECH_COMPILER
 #pragma interrupt_level 1
#endif
 void EZ_Spi_Write(int8 data)
 {
// Changed by Laszlo Kadar on 26.11.05
   u_reg.adat = data;

   MOSI_PIN = 0;
   CLK_PIN = 0;

   MOSI_PIN = u_reg.testreg.bit7 ;
   CLK_PIN = 1;
   CLK_PIN = 0;

   MOSI_PIN = u_reg.testreg.bit6 ;
   CLK_PIN = 1;
   CLK_PIN = 0;

   MOSI_PIN = u_reg.testreg.bit5 ;
   CLK_PIN = 1;
   CLK_PIN = 0;

   MOSI_PIN = u_reg.testreg.bit4 ;
   CLK_PIN = 1;
   CLK_PIN = 0;

   MOSI_PIN = u_reg.testreg.bit3 ;
   CLK_PIN = 1;
   CLK_PIN = 0;

   MOSI_PIN = u_reg.testreg.bit2 ;
   CLK_PIN = 1;
   CLK_PIN = 0;

   MOSI_PIN = u_reg.testreg.bit1 ;
   CLK_PIN = 1;
   CLK_PIN = 0;

   MOSI_PIN = u_reg.testreg.bit0 ;
   CLK_PIN = 1;
   CLK_PIN = 0;
 }
#else
 /*hardware SPI is used*/
 //HW SPI port doesn't supported now!
 int8 Spi_Comm0(void)
 {
 //activate HW SPI port

 //read the data

 //deactivate HW SPI port
 }

 //===============================================================================================

 void EZ_Spi_Write(int data)
 {
 //activate HW SPI port

 //write the data

 //deactivate HW SPI port
 }
#endif