vsc8601_phy.c

linux下atheros的ag7100驱动

{
  vsc8601_phy_print_val_bit_desc (val, "gige_status_ex_2((17 )", gige_status_ex_2_desc);
}

/* Error counts of various types saturate at 0xff */

CEXTERN uint16_t 
vsc8601_phy_read_rx_error_count(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 19);
}

CEXTERN uint16_t 
vsc8601_phy_read_false_carrier_count(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 20);
}

CEXTERN uint16_t 
vsc8601_phy_read_disconnect_count(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 21);
}

CEXTERN uint16_t 
vsc8601_phy_read_ex_crtl_set_1(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 23);
}

static char *ex_crtl_set_1_desc[16*2] = {
  "","", /* 15 */
  "","", /* 14 */
  "","", /* 13 */
  "","", /* 12 */
  "","", /* 11 */
  "","", /* 10 */
  "","", /*  9 */
  "skew-2ns-rx-tx","", /*  8 */
  "","", /*  7 */
  "","", /*  6 */
  "actiphy","", /*  5 */
  "","", /*  4 */
  "","", /*  3 */
  "","", /*  2 */
  "","", /*  1 */
  "","", /*  0 */
};

CEXTERN void 
vsc8601_phy_mii_print_ex_ctrl_set_1(uint16_t val)
{
  vsc8601_phy_print_val_bit_desc (val, "ex_crtl_set_1   (23 )", ex_crtl_set_1_desc);
}

CEXTERN void  
vsc8601_phy_write_ex_crtl_set_1(int unit, uint32_t phy_addr, uint16_t reg)
{
  return vsc8601_phy_mii_write_main(unit, phy_addr, 23, reg);
}

CEXTERN void 
vsc8601_phy_rmw_ex_crtl_set_1(int unit, uint32_t phy_addr, uint32_t mask, uint32_t val)
{
  uint16_t reg = vsc8601_phy_read_ex_crtl_set_1(unit, phy_addr); 
  if (reg == 0xffff)
    return;
  reg &= ~mask;
  reg |=  val;
  vsc8601_phy_write_ex_crtl_set_1(unit, phy_addr, reg);
}

CEXTERN uint16_t 
vsc8601_phy_read_ex_crtl_set_2(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 24);
}

CEXTERN void  
vsc8601_phy_write_ex_crtl_set_2(int unit, uint32_t phy_addr, uint16_t reg)
{
  return vsc8601_phy_mii_write_main(unit, phy_addr, 24, reg);
}

CEXTERN void 
vsc8601_phy_rmw_ex_crtl_set_2(int unit, uint32_t phy_addr, uint32_t mask, uint32_t val)
{
  uint16_t reg = vsc8601_phy_read_ex_crtl_set_2(unit, phy_addr); 
  if (reg == 0xffff)
    return;
  reg &= ~mask;
  reg |=  val;
  vsc8601_phy_write_ex_crtl_set_2(unit, phy_addr, reg);
}

CEXTERN uint16_t  
vsc8601_phy_read_irq_msk(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 25);
}

CEXTERN void 
vsc8601_phy_write_irq_msk(int unit, uint32_t phy_addr, uint16_t reg)
{
  return vsc8601_phy_mii_write_main(unit, phy_addr, 25, reg);
}

CEXTERN uint16_t  
vsc8601_phy_read_irq_status(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 26);
}
static char *irq_status_desc[16*2] = {
  "pending","", /* 15 */
  "speed","", /* 14 */
  "link","", /* 13 */
  "fdx","", /* 12 */
  "auto-err","", /* 11 */
  "auto-cmpl","", /* 10 */
  "inl-pwr","", /*  9 */
  "","", /*  8 */
  "","", /*  7 */
  "","", /*  6 */
  "","", /*  5 */
  "","", /*  4 */
  "","", /*  3 */
  "dwn-shft","", /*  2 */
  "ms-err","", /*  1 */
  "","", /*  0 */
};

CEXTERN void 
vsc8601_phy_mii_print_irq_status(uint16_t val)
{
  vsc8601_phy_print_val_bit_desc (val, "irq_status      (26 )", irq_status_desc);
}

/* RO */

CEXTERN uint16_t 
vsc8601_phy_read_aux_ctrl_status(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 28);
}

static char *aux_ctrl_status_desc[16*2] = {
  "auto-cmplt","", /* 15 */
  "auto-dis","", /* 14 */
  "cross-over","", /* 13 */
  "cd swap","", /* 12 */
  "a-pol","", /* 11 */
  "b-pol","", /* 10 */
  "c-pol","", /*  9 */
  "d-pol","", /*  8 */
  "","", /*  7 */
  "","", /*  6 */
  "fdx","", /*  5 */
  "gige","", /*  4 */
  "100-base-T","", /*  3 */
  "","", /*  2 */
  "sticky","", /*  1 */
  "","", /*  0 */
};

CEXTERN void 
vsc8601_phy_mii_print_aux_ctrl_status(uint16_t val)
{
  vsc8601_phy_print_val_bit_desc (val, "aux_ctrl_status (28 )", aux_ctrl_status_desc);
}

CEXTERN uint16_t 
vsc8601_phy_read_delay_skew_status(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_main(unit, phy_addr, 29);
}

CEXTERN void 
vsc8601_phy_mii_print_delay_skew_status(uint16_t val)
{
  printk(MODULE_NAME": delay_skew_     (29 )=%04x\n", val);
  printk(MODULE_NAME":    pair a delay: %02x\n", (val>>12)&7);
  printk(MODULE_NAME":    pair b delay: %02x\n", (val>> 8)&7);
  printk(MODULE_NAME":    pair c delay: %02x\n", (val>> 4)&7);
  printk(MODULE_NAME":    pair d delay: %02x\n", (val>> 0)&7);
}

/* Extended registers - specific to chips? */

CEXTERN uint16_t 
vsc8601_phy_read_crc_good_counter(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_ex(unit, phy_addr, 18);
}

/* Resistor calibration */

CEXTERN uint16_t 
vsc8601_phy_read_mac_resistor_calibration(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_ex(unit, phy_addr, 19);
}

CEXTERN void 
vsc8601_phy_write_mac_resistor_calibration(int unit, uint32_t phy_addr, uint16_t val)
{
  vsc8601_phy_mii_write_ex(unit, phy_addr, 19, val);
}

CEXTERN void 
vsc8601_phy_rmw_mac_resistor_calibration(int unit, uint32_t phy_addr, uint32_t mask, uint32_t val)
{
  uint16_t reg = vsc8601_phy_read_mac_resistor_calibration(unit, phy_addr); 
  reg &= ~mask;
  reg |=  val;
  vsc8601_phy_write_mac_resistor_calibration(unit, phy_addr, reg);
}

CEXTERN uint16_t 
vsc8601_phy_read_ex_crtl_set_5(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_ex(unit, phy_addr, 27);
}

CEXTERN void 
vsc8601_phy_mii_print_ex_crtl_set_5(uint16_t val)
{
  printk(MODULE_NAME": ex_crtl_set_5   (27E)=%04x\n", val);
  printk(MODULE_NAME":    crs:         %x\n", (val>>12)&7);
  printk(MODULE_NAME":    100  tx amp: %x\n", (val>> 6)&7);
  printk(MODULE_NAME":    gige tx amp: %x\n", (val>> 3)&7);
  printk(MODULE_NAME":    gige edge:   %x\n", (val>> 0)&7);

  if (val & 1<<10)
    printk(MODULE_NAME":   FAR-END-LOOPBACK\n");
}

CEXTERN void
vsc8601_phy_write_ex_crtl_set_5(int unit, uint32_t phy_addr, uint16_t reg)
{
  vsc8601_phy_mii_write_ex(unit, phy_addr, 27, reg);
}

CEXTERN void 
vsc8601_phy_rmw_ex_crtl_set_5(int unit, uint32_t phy_addr, uint32_t mask, uint32_t val)
{
  uint16_t reg = vsc8601_phy_read_ex_crtl_set_5(unit, phy_addr); 
  if (reg == 0xffff)
    return;
  reg &= ~mask;
  reg |=  val;
  vsc8601_phy_write_ex_crtl_set_5(unit, phy_addr, reg);
}

CEXTERN uint16_t 
vsc8601_phy_read_skew_ctrl(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_ex(unit, phy_addr, 28);
}

CEXTERN void 
vsc8601_phy_mii_print_skew_ctrl(uint16_t val)
{
  printk(MODULE_NAME": skew_ctrl       (28E)=%04x\n", val);
  printk(MODULE_NAME":    tx cmp: %x\n", (val>>14)&3);
  printk(MODULE_NAME":    rx cmp: %x\n", (val>>12)&7);
  printk(MODULE_NAME":    jumbo:  %x\n", (val>>10)&7); 
}

CEXTERN void  
vsc8601_phy_write_skew_ctrl(int unit, uint32_t phy_addr, uint16_t reg)
{
  return vsc8601_phy_mii_write_ex(unit, phy_addr, 28, reg);
}

CEXTERN void 
vsc8601_phy_rmw_skew_ctrl(int unit, uint32_t phy_addr, uint32_t mask, uint32_t val)
{
  uint16_t reg = vsc8601_phy_read_skew_ctrl(unit, phy_addr); 
  if (reg == 0xffff)
    return;
  reg &= ~mask;
  reg |=  val;
  vsc8601_phy_write_skew_ctrl(unit, phy_addr, reg);
}

CEXTERN uint16_t 
vsc8601_phy_read_epg_1(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_ex(unit, phy_addr, 29);
}

CEXTERN void  
vsc8601_phy_write_epg_1(int unit, uint32_t phy_addr, uint16_t reg)
{
  return vsc8601_phy_mii_write_ex(unit, phy_addr, 29, reg);
}

CEXTERN void 
vsc8601_phy_rmw_epg_1(int unit, uint32_t phy_addr, uint32_t mask, uint32_t val)
{
  uint16_t reg = vsc8601_phy_read_epg_1(unit, phy_addr); 
  if (reg == 0xffff)
    return;
  reg &= ~mask;
  reg |=  val;
  vsc8601_phy_write_epg_1(unit, phy_addr, reg);
}

CEXTERN uint16_t 
vsc8601_phy_read_epg_2(int unit, uint32_t phy_addr)
{
  return vsc8601_phy_mii_read_ex(unit, phy_addr, 20);
}

CEXTERN void  
vsc8601_phy_write_epg_2(int unit, uint32_t phy_addr, uint16_t reg)
{
  return vsc8601_phy_mii_write_ex(unit, phy_addr, 30, reg);
}

CEXTERN void 
vsc8601_phy_rmw_epg_2(int unit, uint32_t phy_addr, uint32_t mask, uint32_t val)
{
  uint16_t reg = vsc8601_phy_read_epg_2(unit, phy_addr); 
  if (reg == 0xffff)
    return;
  reg &= ~mask;
  reg |=  val;
  vsc8601_phy_write_epg_2(unit, phy_addr, reg);
}

/* Functions */

CEXTERN void 
vsc8601_phy_mii_soft_reset(int unit, uint32_t phy_addr) 
{
  vsc8601_phy_mii_rmw_ctrl(unit, phy_addr, 1<<15, 1<<15);
  udelay(10);
}

CEXTERN void  
vsc8601_phy_mii_set_loopback(int unit, uint32_t phy_addr, int onOff) 
{
  uint32_t   val = onOff ? 1<<14 : 0;	      
  vsc8601_phy_mii_rmw_ctrl(unit, phy_addr, 1<<14, val);
}

CEXTERN void 
vsc8601_phy_mii_set_auto(int unit, uint32_t phy_addr, int onOff) 
{
  uint32_t   val = onOff ? 1<<12 : 0;	  
  vsc8601_phy_mii_rmw_ctrl(unit, phy_addr, 1<<12, val);
}

CEXTERN void 
vsc8601_phy_mii_force_speed(int unit, uint32_t phy_addr, int speed) 
{
  uint32_t val=0;
  if (speed & 1<<0) val |= 1<<6;
  if (speed & 2<<0) val |= 1<<13;
  vsc8601_phy_mii_rmw_ctrl(unit, phy_addr, 1<<6 | 1<<13 , val);
}

CEXTERN void 
vsc8601_phy_mii_restart_auto(int unit, uint32_t phy_addr, int onOff) 
{
  uint32_t   val = onOff ? 1<<9 : 0;	  
  vsc8601_phy_mii_rmw_ctrl(unit, phy_addr, 1<<9, val);
}

CEXTERN void 
vsc8601_phy_mii_set_duplex(int unit, uint32_t phy_addr, int onOff) 
{
  uint32_t   val = onOff ? 1<<8 : 0;	  
  vsc8601_phy_mii_rmw_ctrl(unit, phy_addr, 1<<8, val);
}

/* IEEE GIGE extended control */

CEXTERN void 
vsc8601_phy_set_gige_test_normal(int unit, uint32_t phy_addr) 
{
  vsc8601_phy_rmw_gige_ctrl(unit, phy_addr, 7<<13, 0<<13);
}

CEXTERN void 
vsc8601_phy_set_gige_test_waveform(int unit, uint32_t phy_addr) 
{
  vsc8601_phy_rmw_gige_ctrl(unit, phy_addr, 7<<13, 1<<13);
}

CEXTERN void 
vsc8601_phy_set_gige_test_jitter_master(int unit, uint32_t phy_addr) 
{
  vsc8601_phy_rmw_gige_ctrl(unit, phy_addr, 7<<13, 2<<13);
}

CEXTERN void 
vsc8601_phy_set_gige_test_jitter_slave(int unit, uint32_t phy_addr) 
{
  vsc8601_phy_rmw_gige_ctrl(unit, phy_addr, 7<<13, 3<<13);
}

CEXTERN void 
vsc8601_phy_set_gige_test_distortion(int unit, uint32_t phy_addr) 
{