ag7100.h

linux下atheros的ag7100驱动

#define AG7100_TX_STATUS_PKT_SENT       0x1
#define AG7100_TX_STATUS_URN            0x2
#define AG7100_TX_STATUS_BUS_ERROR      0x8

#define AG7100_RXE                      (1 << 0)

#define AG7100_RX_STATUS_PKTCNT_MASK    0xff0000
#define AG7100_RX_STATUS_PKT_RCVD       (1 << 0)
#define AG7100_RX_STATUS_OVF            (1 << 2)
#define AG7100_RX_STATUS_BUS_ERROR      (1 << 3)

/*
 * Int and int mask
 */
#define AG7100_INTR_TX                  (1 << 0)
#define AG7100_INTR_TX_URN              (1 << 1)
#define AG7100_INTR_TX_BUS_ERROR        (1 << 3)
#define AG7100_INTR_RX                  (1 << 4)
#define AG7100_INTR_RX_OVF              (1 << 6)
#define AG7100_INTR_RX_BUS_ERROR        (1 << 7)

/*
 * MII registers
 */
#define AG7100_MAC_MII_MGMT_CFG         0x20
#define AG7100_MGMT_CFG_CLK_DIV_20      0x06
#define AG7100_MII_MGMT_CMD             0x24
#define AG7100_MGMT_CMD_READ            0x1
#define AG7100_MII_MGMT_ADDRESS         0x28
#define AG7100_ADDR_SHIFT               8
#define AG7100_MII_MGMT_CTRL            0x2c
#define AG7100_MII_MGMT_STATUS          0x30
#define AG7100_MII_MGMT_IND             0x34
#define AG7100_MGMT_IND_BUSY            (1 << 0)
#define AG7100_MGMT_IND_INVALID         (1 << 2)
#define AG7100_GE_MAC_ADDR1             0x40
#define AG7100_GE_MAC_ADDR2             0x44
#define AG7100_MII0_CONTROL             0x18070000

/*
 * Everything but TX
 */
#define AG7100_INTR_MASK    (AG7100_INTR_RX | AG7100_INTR_RX_OVF |  \
                             AG7100_INTR_RX_BUS_ERROR |             \
                             AG7100_INTR_TX_BUS_ERROR              \
                             /*| AG7100_INTR_TX_URN | AG7100_INTR_TX*/)

#define ag7100_reg_rd(_mac, _reg)                                       \
            (ar7100_reg_rd((_mac)->mac_base + (_reg)))

#define ag7100_reg_wr(_mac, _reg, _val)                                 \
                ar7100_reg_wr((_mac)->mac_base + (_reg), (_val));

/*
 * The no flush version
 */
#define ag7100_reg_wr_nf(_mac, _reg, _val)                             \
                ar7100_reg_wr_nf((_mac)->mac_base + (_reg), (_val));

#define ag7100_reg_rmw_set(_mac, _reg, _mask)                           \
                 ar7100_reg_rmw_set((_mac)->mac_base + (_reg), (_mask));

#define ag7100_reg_rmw_clear(_mac, _reg, _mask)                          \
                 ar7100_reg_rmw_clear((_mac)->mac_base + (_reg), (_mask));


#define ag7100_desc_dma_addr(_r, _ds)                                   \
    (u32)((ag7100_desc_t *)(_r)->ring_desc_dma + ((_ds) - ((_r)->ring_desc)))


/*
 * tx/rx stop start
 */
#define ag7100_tx_stopped(_mac)                                         \
    (!(ag7100_reg_rd((_mac), AG7100_DMA_TX_CTRL) & AG7100_TXE))

#define ag7100_rx_start(_mac)                                           \
    ag7100_reg_wr((_mac), AG7100_DMA_RX_CTRL, AG7100_RXE)

#define ag7100_rx_stop(_mac)                                            \
    ag7100_reg_wr((_mac), AG7100_DMA_RX_CTRL, 0)

#define ag7100_tx_start(_mac)                                           \
    ag7100_reg_wr((_mac), AG7100_DMA_TX_CTRL, AG7100_TXE)

#define ag7100_tx_stop(_mac)                                            \
    ag7100_reg_wr((_mac), AG7100_DMA_TX_CTRL, 0)

static inline int
ag7100_ndesc_unused(ag7100_mac_t *mac, ag7100_ring_t *ring)
{
    int head = ring->ring_head, tail = ring->ring_tail;

    return ((tail > head ? 0 : ring->ring_nelem) + tail - head);
}

static inline int ag7100_rx_ring_full(ag7100_mac_t *mac)
{
    ag7100_ring_t *r    = &mac->mac_rxring;
    int            tail = r->ring_tail;

    return ((r->ring_head == tail) && !r->ring_buffer[tail].buf_pkt);
}

#define ag7100_ring_incr(_idx)                                             \
        if(unlikely(++(_idx) == r->ring_nelem)) (_idx) = 0;

/*
 * ownership of descriptors between DMA and cpu
 */
#define ag7100_rx_owned_by_dma(_ds)     ((_ds)->is_empty == 1)
#define ag7100_rx_give_to_dma(_ds)      ((_ds)->is_empty = 1)
#define ag7100_tx_owned_by_dma(_ds)     ((_ds)->is_empty == 0)
#define ag7100_tx_give_to_dma(_ds)      ((_ds)->is_empty = 0)
#define ag7100_tx_own(_ds)              ((_ds)->is_empty = 1)

/*
 * Interrupts 
 * ----------
 */
#define ag7100_get_isr(_mac) ag7100_reg_rd((_mac), AG7100_DMA_INTR);
#define ag7100_int_enable(_mac)                                         \
    ag7100_reg_wr(_mac, AG7100_DMA_INTR_MASK, AG7100_INTR_MASK)

#define ag7100_int_disable(_mac)                                        \
    ag7100_reg_wr(_mac, AG7100_DMA_INTR_MASK, 0)
/*
 * ACKS:
 * - We just write our bit - its write 1 to clear.
 * - These are not rmw's so we dont need locking around these.
 * - Txurn and rxovf are not fastpath and need consistency, so we use the flush
 *   version of reg write.
 * - ack_rx is done every packet, and is largely only for statistical purposes;
 *   so we use the no flush version and later cause an explicite flush.
 */
#define ag7100_intr_ack_txurn(_mac)                                           \
    ag7100_reg_wr((_mac), AG7100_DMA_TX_STATUS, AG7100_TX_STATUS_URN);
#define ag7100_intr_ack_rx(_mac)                                              \
    ag7100_reg_wr_nf((_mac), AG7100_DMA_RX_STATUS, AG7100_RX_STATUS_PKT_RCVD);
#define ag7100_intr_ack_rxovf(_mac)                                           \
    ag7100_reg_wr((_mac), AG7100_DMA_RX_STATUS, AG7100_RX_STATUS_OVF);
/*
 * Not used currently
 */
#define ag7100_intr_ack_tx(_mac)                                              \
    ag7100_reg_wr((_mac), AG7100_DMA_TX_STATUS, AG7100_TX_STATUS_PKT_SENT);
#define ag7100_intr_ack_txbe(_mac)                                            \
    ag7100_reg_wr((_mac), AG7100_DMA_TX_STATUS, AG7100_TX_STATUS_BUS_ERROR);
#define ag7100_intr_ack_rxbe(_mac)                                            \
    ag7100_reg_wr((_mac), AG7100_DMA_RX_STATUS, AG7100_RX_STATUS_BUS_ERROR);

/*
 * Enable Disable. These are Read-Modify-Writes. Sometimes called from ISR
 * sometimes not. So the caller explicitely handles locking.
 */
#define ag7100_intr_disable_txurn(_mac)                                     \
    ag7100_reg_rmw_clear((_mac), AG7100_DMA_INTR_MASK, AG7100_INTR_TX_URN);

#define ag7100_intr_enable_txurn(_mac)                                      \
    ag7100_reg_rmw_set((_mac), AG7100_DMA_INTR_MASK, AG7100_INTR_TX_URN);

#define ag7100_intr_enable_tx(_mac)                                      \
    ag7100_reg_rmw_set((_mac), AG7100_DMA_INTR_MASK, AG7100_INTR_TX);

#define ag7100_intr_disable_tx(_mac)                                     \
    ag7100_reg_rmw_clear((_mac), AG7100_DMA_INTR_MASK, AG7100_INTR_TX);

#define ag7100_intr_disable_recv(_mac)                                      \
    ag7100_reg_rmw_clear(mac, AG7100_DMA_INTR_MASK,                         \
                        (AG7100_INTR_RX | AG7100_INTR_RX_OVF));

#define ag7100_intr_enable_recv(_mac)                                      \
    ag7100_reg_rmw_set(mac, AG7100_DMA_INTR_MASK,                          \
                        (AG7100_INTR_RX | AG7100_INTR_RX_OVF));

static inline void ag7100_start_rx_count(ag7100_mac_t *mac)
{
    if (mac->mac_unit == 0) {
        printk("Writing %d\n", PERF_CTL_GE0_PKT_CNT);
        ar7100_perf0_ctl(PERF_CTL_GE0_PKT_CNT);
    }
    else {
        printk("Writing %d\n", PERF_CTL_GE1_PKT_CNT);
        ar7100_perf1_ctl(PERF_CTL_GE1_PKT_CNT);
    }
}

static inline uint32_t ag7100_get_rx_count(ag7100_mac_t *mac)
{
    if (mac->mac_unit == 0) {
        return (ar7100_reg_rd(AR7100_PERF0_COUNTER));
    }
    else {
        return (ar7100_reg_rd(AR7100_PERF1_COUNTER));
    }
}
/*
 * link settings
 */
static inline void ag7100_set_mac_duplex(ag7100_mac_t *mac, int fdx)
{
    if (fdx) {
        ag7100_reg_rmw_set(mac, AG7100_MAC_CFG2, AG7100_MAC_CFG2_FDX);
    }
    else {
        ag7100_reg_rmw_clear(mac, AG7100_MAC_CFG2, AG7100_MAC_CFG2_FDX);
    }
}

static inline void ag7100_set_mac_if(ag7100_mac_t *mac, int is_1000)
{
    ag7100_reg_rmw_clear(mac, AG7100_MAC_CFG2, (AG7100_MAC_CFG2_IF_1000| 
                         AG7100_MAC_CFG2_IF_10_100));
    if (is_1000) {                                                        
        ag7100_reg_rmw_set(mac, AG7100_MAC_CFG2, AG7100_MAC_CFG2_IF_1000);
        ag7100_reg_rmw_set(mac, AG7100_MAC_FIFO_CFG_5, AG7100_BYTE_PER_CLK_EN);                          
    }                                                                        
    else {                                                                   
        ag7100_reg_rmw_set(mac, AG7100_MAC_CFG2, AG7100_MAC_CFG2_IF_10_100);
        ag7100_reg_rmw_clear(mac,AG7100_MAC_FIFO_CFG_5, AG7100_BYTE_PER_CLK_EN);
    }                                                                        
}

static inline void ag7100_set_mac_speed(ag7100_mac_t *mac, int is100)
{
    if (is100) {
        ag7100_reg_rmw_set(mac, AG7100_MAC_IFCTL, AG7100_MAC_IFCTL_SPEED); 
    }
    else {
        ag7100_reg_rmw_clear(mac, AG7100_MAC_IFCTL, AG7100_MAC_IFCTL_SPEED);
    }
}

uint16_t ag7100_mii_read(int unit, uint32_t phy_addr, uint8_t reg);
void ag7100_mii_write(int unit, uint32_t phy_addr, uint8_t reg, uint16_t data);

#endif