📄 int.s.bak
字号:
;*
;* INPUTS
;*
;* None
;*
;* OUTPUTS
;*
;* None
;*
;* HISTORY
;*
;* NAME DATE REMARKS
;*
;*
;************************************************************************
; EXPORT INT_Prefetch_Abort
INT_Prefetch_Abort
MOV r0, lr
B INT_Prefetch_Abort
;************************************************************************
;*
;* FUNCTION
;*
;* INT_Data_Abort
;*
;* DESCRIPTION
;*
;* This is a stub for the Data Abort Interrupt
;*
;*
;* CALLED BY
;*
;* None
;*
;* CALLS
;*
;* None
;*
;* INPUTS
;*
;* None
;*
;* OUTPUTS
;*
;* None
;*
;* HISTORY
;*
;* NAME DATE REMARKS
;*
;*
;************************************************************************
; EXPORT INT_Data_Abort
INT_Data_Abort
STMDB sp!,{r0-r3,lr}
LDMIA sp!,{r0-r3,lr}
BX LR
B INT_Data_Abort
;************************************************************************
;*
;* FUNCTION
;*
;* INT_Reserved
;*
;* DESCRIPTION
;*
;* This is a stub for the Reserved Interrupt
;*
;*
;* CALLED BY
;*
;* None
;*
;* CALLS
;*
;* None
;*
;* INPUTS
;*
;* None
;*
;* OUTPUTS
;*
;* None
;*
;* HISTORY
;*
;* NAME DATE REMARKS
;*
;*
;************************************************************************
; EXPORT INT_Reserved
INT_Reserved
MOV r0, lr
B INT_Reserved
;************************************************************************
;*
;* FUNCTION
;*
;* INT_IRQ
;*
;* DESCRIPTION
;*
;* This routine is the board-specific section for
;* level 1 interrupt handling
;*
;* CALLED BY
;*
;* None
;*
;* CALLS
;*
;* TMT_Timer_Interrupt
;*
;* INPUTS
;*
;* None
;*
;*
;* OUTPUTS
;*
;* None
;*
;* HISTORY
;*
;* NAME DATE REMARKS
;*
;* B. Ronquillo 05-10-00 Created initial version 1.0
;*
;************************************************************************
INT_IRQ
; ARM Core Check
STMDB sp!, {r1}
MRS r1, SPSR
TST r1, #IRQ_BIT
LDMIA sp!, {r1}
SUBNES pc,lr,#4
STMDB sp!,{r0-r4} ; Save r0-r4 on temporary IRQ stack
SUB lr,lr,#4 ; Adjust IRQ return address
;Modified by tianqiang, 09-07-2004
;delete codes for timer3 handling
;********************************
;* Begin Hardware Specific Code *
;********************************
;INT_NEXT
LDR r3, INT_CNTRL_BASE_1 ; load Interrupt Control Base
LDR r4, [r3,#INT_IRQ0_ENABLESET] ; Get enable register value
;******************************
;* End Hardware Specific Code *
;******************************
STMDB sp!,{r4} ; Put the enable register value on the IRQ stack
MVN r4,#0 ; Start with 0xFFFFFFFF to allow nesting of interrupts
;********************************
;* Begin Hardware Specific Code *
;********************************
LDR r2, [r3,#INT_IRQ0_STATUS] ; Read Pending reg
;******************************
;* End Hardware Specific Code *
;******************************
LDR r3, IRQ_Priority ; Get the Priority table address
IRQ_VECTOR_LOOP
LDR r0, [r3,#0] ; Load first vector to be checked from priority table
MOV r1, #1 ; Build mask
MOV r1, r1, LSL r0 ; Use vector number to set mask to correct bit position
TST r1, r2 ; Test if pending bit is set
BNE IRQ_VECTOR_FOUND ; If bit is set, branch to found section...
BIC r4,r4,r1 ; Clear mask bit to keep higher priority ints active
ADD r3, r3, #4 ; Move to next word in the priority table
ADR r0, Priority_End ; Load the end address for the priority table
CMP r0, r3 ; Make sure not at the end of the table (shouldn't happen!)
BNE IRQ_VECTOR_LOOP ; Continue to loop if not at the end of the table
; No bits in pending register set, restore registers and exit interrupt servicing
ADD sp,sp,#4 ; Adjust sp above IRQ enable value
LDMIA sp!,{r0-r4} ; Restore r0-r4
STMDB sp!,{lr} ; Put return address for IRQ on stack
LDMIA sp!,{pc}^ ; return to the point of the exception and restore SPSR
IRQ_VECTOR_FOUND
;********************************
;* Begin Hardware Specific Code *
;********************************
LDR r3, INT_CNTRL_BASE_1 ; load Interrupt Control Base
; MVN r2, r1 ; Get the inverse of the interrupt vector
; STR r2, [r3,#INT_IRQ0_STATUS] ; Write a zero to the interrupt being handled
LDR r2, [r3,#INT_IRQ0_ENABLESET] ; Read the Mask reg
; ORR r4, r2, r4 ; Turn off lower priority pending bits and currently masked bits
; STR r4, [r3,#INT_IRQ0_ENABLESET] ; Disable(Mask) all lower priority interrupts and currently masked interrupts
BIC r2, r2, r1 ; Clear the pending interrupt
; STR r2, [r3,#INT_IRQ0_ENABLECLR] ; Write a 1 to the interrupt clear register
STR r2, [r3,#INT_IRQ0_ENABLESET] ; Write a 1 to the interrupt enable register
;******************************
;* End Hardware Specific Code *
;******************************
LDR r3, IRQ_Vectors ; Get IRQ vector table address
MOV r2, r0, LSL #2 ; Multiply vector by 4 to get offset into table
ADD r3, r3, r2 ; Adjust vector table address to correct offset
LDR r2, [r3,#0] ; Load branch address from vector table
MOV PC, r2 ; Jump to correct branch location based on vector table
; END: INT_IRQ
;*************************************************************
;*
;* FUNCTION
;*
;* INT_FIQ
;*
;* DESCRIPTION
;*
;* This routine is the board-specific section for
;* FIQ interrupt handling
;*
;* CALLED BY
;*
;* None
;*
;* CALLS
;*
;* None
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -