📄 int.s.bak
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Current_Thread DCD TCD_Current_Thread ;add by lilin
;add by tianqiang
Idle_Task_Stack_Mem DCD INT_Idle_Task_Stack_Mem
Idle_Task_Stack_Ptr DCD STD_Idle_Task_Stack_Ptr
;************************************************************************
;*
;* FUNCTION
;*
;* INT_Initialize
;*
;* DESCRIPTION
;*
;* This function sets up the global system stack variable and
;* transfers control to the target independent initialization
;* function INC_Initialize. Responsibilities of this function
;* include the following:
;*
;* - Setup necessary processor/system control registers
;* - Initialize the vector table
;* - Setup the system stack pointers
;* - Setup the timer interrupt
;* - Calculate the timer HISR stack and priority
;* - Calculate the first available memory address
;* - Transfer control to INC_Initialize to initialize all of
;* the system components.
;*
;* Major Revision:
;*
;* M. Kyle Craig, Accelerated Technology, Inc.
;*
;*
;*
;*
;* CALLED BY
;*
;* Nothing. This function is the ENTRY point for Nucleus PLUS.
;*
;* CALLS
;*
;* INC_Initialize Common initialization
;*
;* INPUTS
;*
;* None
;*
;* OUTPUTS
;*
;* None
;*
;* HISTORY
;*
;* NAME DATE REMARKS
;*
;* W. Lamie 08-27-1994 Created initial version 1.0
;* D. Lamie 08-27-1994 Verified version 1.0
;*
;************************************************************************
;VOID INT_Initialize(void)
;{
ENTRY
; EXPORT _c_int00
;_c_int00
EXPORT INT_Initialize
INT_Initialize
; Insure that the processor is in supervisor mode.
MSR CPSR_c, #SUP_MODE:OR:LOCKOUT ; Set the supervisor mode and
;Insure IRQ/FIQ interrupts are locked out
; Turn-on the I-Cache for the TI 925T Processor
; MRC p15,#0,r1,C1,C0,#0 ; Read the control register.
; ORR r1,r1,#0x1000 ; Set the I bit to enable Instruction Cache
; NOP
; MCR p15,#0,r1,C1,C0,#0 ; Write the control register.
IMPORT Cache_Init
BL Cache_Init
; Setup the vectors loaded flag to indicate to other routines in the
; system whether or not all of the default vectors have been loaded.
; If INT_Loaded_Flag is 1, all of the default vectors have been loaded.
; Otherwise, if INT_Loaded_Flag is 0, registering an LISR cause the
; default vector to be loaded. In the ARM60 this variable is always
; set to 1. All vectors must be setup by this function.
; INT_Loaded_Flag = 0;
MOV r0,#1 ; All vectors are assumed loaded
LDR r1,Loaded_Flag ; Build address of loaded flag
STR r0,[r1,#0] ; Initialize loaded flag
; Initialize the system stack pointers. This is done after the BSS is
; clear because the TCD_System_Stack pointer is a BSS variable! It is
; assumed that available memory starts immediately after the end of the
; BSS section.
LDR r10,System_Stk_Limit ; Pickup the system stack limit (bottom of system stack)
LDR r3,System_Limit ; Pickup sys stack limit addr
STR r10,[r3, #0] ; Save stack limit
LDR sp,System_Stack_SP ; Set-up the system stack pointer
LDR r3,System_Stack ; Pickup system stack address
STR sp,[r3, #0] ; Save stack pointer
MSR CPSR_c, #IRQ_MODE:OR:LOCKOUT ; Set the IRQ mode
LDR sp,IRQ_Stack_SP ; Setup IRQ stack pointer
MSR CPSR_c, #FIQ_MODE:OR:LOCKOUT ; Set the FIQ mode
LDR sp,FIQ_Stack_SP ; Setup FIQ stack pointer
MSR CPSR_c, #SUP_MODE:OR:LOCKOUT ; return to supervisor mode
; Define the global data structures that need to be initialized by this
; routine. These structures are used to define the system timer
; management HISR.
; TMD_HISR_Stack_Ptr = (VOID *) r2;
; TMD_HISR_Stack_Size = TIMER_SIZE;
; TMD_HISR_Priority = TIMER_PRIORITY;
LDR r2,HISR_Stack_Mem ; Get HISR stack memory address
LDR r3,HISR_Stack_Ptr ; Pickup variable's address
STR r2,[r3, #0] ; Setup timer HISR stack pointer
MOV r1,#HISR_STACK_SIZE ; Pickup the timer HISR stack size
LDR r3,HISR_Stack_Size ; Pickup variable's address
STR r1,[r3, #0] ; Setup timer HISR stack size
MOV r1,#HISR_PRIORITY ; Pickup timer HISR priority (0-2)
LDR r3,HISR_Priority ; Pickup variable's address
STR r1,[r3, #0] ; Setup timer HISR priority
;add by tianqiang
LDR r2,Idle_Task_Stack_Mem ; Get idle task stack memory address
LDR r3,Idle_Task_Stack_Ptr ; Pickup variable's address
STR r2,[r3, #0] ; Setup idle task stack pointer
;add end
; Make a call to begin all board specific initialization.
; Begin with Initializing the Vector table and replacing
; default interrupts with Plus IRQs. Then setup the timer
; and begin the system clock.
IF :DEF: NU_ROM_SUPPORT
BL INT_Timer_Initialize ; Initialize the timer
ELSE
BL INT_Install_Vector_Table ; Install the vector table
BL INT_Timer_Initialize ; Initialize the timer
ENDIF
; Call INC_Initialize with a pointer to the first available memory
; address after the compiler's global data. This memory may be used
; by the application.
; INC_Initialize(first_available_memory);
LDR r0,First_Avail_Mem ; Get address of first available memory
B INC_Initialize ; to high-level initialization
;}
;************************************************************************
;*
;* FUNCTION
;*
;* INT_Vectors_Loaded
;*
;* DESCRIPTION
;*
;* This function returns the flag that indicates whether or not
;* all the default vectors have been loaded. If it is false,
;* each LISR register also loads the ISR shell into the actual
;* vector table.
;*
;*
;* Major Revision:
;*
;* M. Kyle Craig, Accelerated Technology, Inc.
;*
;*
;*
;* CALLED BY
;*
;* TCC_Register_LISR Register LISR for vector
;*
;* CALLS
;*
;* None
;*
;* INPUTS
;*
;* None
;*
;* OUTPUTS
;*
;* None
;*
;* HISTORY
;*
;* NAME DATE REMARKS
;*
;* W. Lamie 08-27-1994 Created initial version 1.0
;* D. Lamie 08-27-1994 Verified version 1.0
;*
;************************************************************************
;INT INT_Vectors_Loaded(void)
;{
; EXPORT INT_Vectors_Loaded
;INT_Vectors_Loaded ; Dual-state interworking veneer
; CODE16
; BX pc
; NOP
; CODE32
; B _INT_Vectors_Loaded
EXPORT INT_Vectors_Loaded
INT_Vectors_Loaded
; Just return the loaded vectors flag.
; return(INT_Loaded_Flag);
LDR r0,Loaded_Flag ; Get the address
LDR r0,[r0,#0] ; Load current value
BX lr ; Return to caller
;}
;************************************************************************
;*
;* FUNCTION
;*
;* INT_Setup_Vector
;*
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