asm_defs.s

Nuclues嵌入式RTOS源码

;INT_IRQ54_32K_TIMER         .equ    54    ; 32K Timer
;INT_IRQ55_MMC               .equ    55    ; MMC Interrupt  
;INT_IRQ56_ULPD              .equ    56    ; ULPD GuagingInterrupt
;INT_IRQ57_RTC_TIMER         .equ    57    ; RTC Timer Interrupt
;INT_IRQ58_RTC_ALARM         .equ    58    ; RTC Alarm Interrupt
;INT_IRQ59_RESERVED          .equ    59    ; Reserved
;INT_IRQ60_DSP_MMU           .equ    60    ; DSP MMU Interrupt  
;INT_IRQ61_USB_ISO           .equ    61    ; USB Function ISO On Interrupt  
;INT_IRQ62_USB_NON_ISO       .equ    62    ; USB Function NON ISO On Interrupt  
;INT_IRQ63_McBSP2_RX_OVER    .equ    63    ; McBSP2 Receive Overflow Interrupt  

;**********************************
;* NUCLEUS FIQ TIMER CONSTANTS    *
;**********************************
; Page 6-5,6 of the OMAP Dual Core Processor Technical Reference Manual
; Based off TIMER 1
IRQ_TIMER_BASE              DCD   0x2001E800        ; Define base for all timer registers
IRQ_TIMER1_LOAD             EQU   0x100              ; Offset of timer load register from base
IRQ_TIMER1_VALUE            EQU   0x104
IRQ_TIMER1_CTRL             EQU   0x108              ; Must set this before a timer 
                                                    ; is used (CNTL TIMER Reg)
IRQ_TIMER1_CLR              EQU   0x10C

IRQ_TIMER_PTV               EQU   0x00000004        ; Prescale clock by 16
IRQ_TIMER_ST                EQU   0x00000080        ; Bit 0 to start timer
IRQ_TIMER_AR                EQU   0x00000000        ; Bit 1 to auto-reload
IRQ_TIMER_CLOCK             EQU   20000000          ; Clock used by timer
IRQ_TIMER_PRESCALE          EQU   16               
IRQ_TICKS_PER_SEC           EQU   100


; Calculate timer count value based on timer clock, timer pre-scale and the number
; of timer ticks per second (100 = 10 ms timer interrupt)
; The equation for this count value is:  count = (CLOCK/PRESCALE) * .010 seconds 

IRQ_TIMER_COUNT             EQU  (IRQ_TIMER_CLOCK/IRQ_TIMER_PRESCALE) / IRQ_TICKS_PER_SEC

IRQ_TIMER_LOAD_VAL          DCD  IRQ_TIMER_COUNT   ; 32-bit count 
FIQ_TIMER_RESET             EQU  0x00000000


; Timer 1 interrupt bits 
FIQ_TIMER_IRQ               EQU  26
IRQ_TIMER_MASK              EQU  0x00000040
FIQ_TIMER_ILR               EQU  0x0001


;******************************
;* NUCLEUS TIMER CONSTANTS    *
;******************************
; Page 6-5,6 of the OMAP Dual Core Processor Technical Reference Manual
; Based off TIMER 2
CNTL_TIMER_BASE             DCD   0x2001E800        ; Define base for all timer registers
TIMER1_LOAD                 EQU   0x14              ; Offset of timer load register from base
TIMER1_VALUE                EQU   0x18
TIMER1_CTRL                 EQU   0x1c              ; Must set this before a timer 
TIMER1_CLR                  EQU   0x20
TIMER1_STATUS		    EQU   0x24
                                                    
TIMER_ST                    EQU   0x00000001        ; Bit 1 to enable timer
TIMER_AR                    EQU   0x00000002        ; Bit 1 to auto-reload
TIMER_CLOCK                 EQU   32000             ; Clock used by timer
TIMER_PRESCALE              EQU   1
;TIMER_TICKS_PER_SEC         EQU   100		    ; 10ms
;TIMER_TICKS_PER_SEC         EQU   1000		    ; 1ms
TIMER_TICKS_PER_SEC         EQU   500		    ; 2ms

; Calculate timer count value based on timer clock, timer pre-scale and the number
; of timer ticks per second (100 = 10 ms timer interrupt)
; The equation for this count value is:  count = (CLOCK/PRESCALE) * .010 seconds 

TIMER_COUNT                 EQU   (TIMER_CLOCK/TIMER_PRESCALE) / TIMER_TICKS_PER_SEC

TIMER_LOAD_VAL              DCD   TIMER_COUNT       ; 32-bit count
TIMER_RESET                 EQU   0x00000000


; Timer interrupt bits
TIMER_IRQ                   EQU   30
TIMER_MASK                  EQU   0x200
TIMER_ILR                   EQU   0x0000 

CPR_CNTL_BASE     	    DCD   0x2001C400      ; Base address for CPR 
CPR_TIMER_CLK               EQU   0x0C            ; CPR Timer Clock Register
TIMER1_CLK		    EQU   0x18		  ; Select Timer1 Clock to 32K

DPLL_CNTL_BASE              EQU   0xFFFECF00      ; Base address for MPU Clock Control Register
DPLL_ENABLE_MASK            EQU   0x0010          ; Mask out PLL ENABLE bit 
DPLL_CLOCK_MULT             DCD   0x0390          ; DPLL Mult Value (7*12MHz)=84MHz = TIMER_CLOCK

   
;******************************
;* MONITOR CONSTANTS          *
;******************************
; Traffic Controller Registers
EMIFS_CS0_CONFIG             DCD   0xFFFECC10
EMIFS_CS1_CONFIG             DCD   0xFFFECC14
EMIFS_CS2_CONFIG             DCD   0xFFFECC18
EMIFS_CS3_CONFIG             DCD   0xFFFECC1C
EMIFF_SDRAM_CONFIG           DCD   0xFFFECC20
EMIFF_MRS                    DCD   0xFFFECC24

CS0_VALUE                    DCD   0x00203339
CS1_VALUE                    DCD   0x1139
CS2_VALUE                    DCD   0x1139
CS3_VALUE                    DCD   0x1139
SDRAM_VALUE                  DCD   0x0000BCF4
MRS_VALUE                    DCD   0x00000027

WDOG_TIMER_MODE              DCD   0xFFFEC808
WDOG_DISABLE_F5              DCD   0x00F5
WDOG_DISABLE_A0              DCD   0x00A0


;********************************************
;*  TC_TCB and TC_HCB STRUCT OFFSET DEFINES *
;********************************************
TC_CREATED              EQU      0x0000         ; Node for linking to created task list
TC_ID                   EQU      0x000C         ; Internal TCB ID
TC_NAME                 EQU      0x0010         ; Task name
TC_STATUS               EQU      0x0018         ; Task status
TC_DELAYED_SUSPEND      EQU      0x0019         ; Delayed task suspension
TC_PRIORITY             EQU      0x001A         ; Task priority
TC_PREEMPTION           EQU      0x001B         ; Task preemption enable
TC_SCHEDULED            EQU      0x001C         ; Task scheduled count
TC_CUR_TIME_SLICE       EQU      0x0020         ; Current time slice
TC_STACK_START          EQU      0x0024         ; Stack starting address
TC_STACK_END            EQU      0x0028         ; Stack ending address
TC_STACK_POINTER        EQU      0x002C         ; Task stack pointer
TC_STACK_SIZE           EQU      0x0030         ; Task stack's size
TC_STACK_MINIMUM        EQU      0x0034         ; Minimum stack size
TC_CURRENT_PROTECT      EQU      0x0038         ; Current protection
TC_SAVED_STACK_PTR      EQU      0x003C         ; Previous stack pointer
TC_ACTIVE_NEXT          EQU      0x003C         ; Next activated HISR
TC_TIME_SLICE           EQU      0x0040         ; Task time slice value
TC_ACTIVATION_COUNT     EQU      0x0040         ; Activation counter
TC_HISR_ENTRY           EQU      0x0044         ; HISR entry function
TC_HISR_SU_MODE         EQU      0x0058         ; Sup/User mode indicator for HISRs
TC_HISR_MODULE          EQU      0x005C         ; Module identifier for HISR's
TC_SU_MODE              EQU      0x00A8         ; Sup/User mode indicator for Tasks
TC_MODULE               EQU      0x00AC         ; Module identifier for Tasks 

	END


; End of low-level initialization constants.

; /******** END ASM_DEFS.ASH ********/