asm_defs.s

Nuclues嵌入式RTOS源码

;************************************************************************
;*                                                                       
;*               Copyright Mentor Graphics Corporation 2002              
;*                         All Rights Reserved.                          
;*                                                                       
;* THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS  
;* THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS   
;* SUBJECT TO LICENSE TERMS.                                             
;*                                                                       
;************************************************************************
;************************************************************************
;*                                                                       
;* FILE NAME                            VERSION                          
;*                                                                       
;*      asm_defs.inc            Nucleus PLUS\ARM925\Code Composer 1.14.1 
;*                                                                       
;* COMPONENT                                                             
;*                                                                       
;*      IN - Initialization                                              
;*                                                                       
;* DESCRIPTION                                                           
;*                                                                       
;*      This file contains the target processor dependent initialization 
;*      values used in int.s, tct.s, and tmt.s                      
;*                                                                       
;* HISTORY                                                               
;*                                                                       
;*         NAME            DATE                    REMARKS               
;*                                                                       
;*      B. Ronquillo     08-28-2002          Released version 1.13.1      
;*                                                                       
;************************************************************************
;**********************************
;* BOARD INITIALIZATION CONSTANTS *
;**********************************
; Begin define constants used in low-level initialization.
LOCKOUT                    EQU	   0xC0   ; Interrupt lockout value
LOCK_MSK                   EQU     0xC0   ; Interrupt lockout mask value
MODE_MASK                  EQU     0x1F   ; Processor Mode Mask
SUP_MODE                   EQU     0x13   ; Supervisor Mode (SVC)
IRQ_MODE                   EQU     0x12   ; Interrupt Mode (IRQ)
IRQ_MODE_OR_LOCKOUT        EQU     0xD2   ; Combined IRQ_MODE OR'ed with LOCKOUT
FIQ_MODE                   EQU     0x11   ; Fast Interrupt Mode (FIQ)
IRQ_BIT                    EQU     0x80   ; Interrupt bit of CPSR and SPSR
;IRQ_BIT                    EQU     0x40   ; Interrupt bit of CPSR and SPSR
FIQ_BIT                    EQU     0x40   ; Interrupt bit of CPSR and SPSR
IRQ_BIT_OR_FIQ_BIT         EQU     0xC0   ; IRQ or FIQ interrupt bit of CPSR and SPSR

IRQStatus                  EQU     0x00

IRQ_STACK_SIZE             EQU     128     ; Number of bytes in IRQ stack
                                            ; -Note that the IRQ interrupt,
                                            ; by default, is managed by 
                                            ; Nucleus PLUS.  Only several
                                            ; words are actually used.  The 
                                            ; system stack is what will 
                                            ; actually be used for Nuclues
                                            ; PLUS managed IRQ interrupts.

FIQ_STACK_SIZE              EQU    128     ; Number of bytes in FIQ stack.
                                            ; This value is application 
                                            ; specific.  By default, Nucleus
                                            ; does not manage FIQ interrupts
                                            ; and furthermore, leaves them
                                            ; enabled virtually all the time.


IRQ_CLEAR_OFFSET            EQU   0x0      ; Clears IRQ register
FIQ_CLEAR_OFFSET            EQU   0x1      ; Clears FIQ register

;*****************************
;* NUCLEUS SYSTEM CONSTANTS  *
;*****************************
SYSTEM_STACK_SIZE           EQU    1024    ; Define the system stack size
HISR_STACK_SIZE             EQU    2048    ; Define timer HISR stack size

HISR_PRIORITY               EQU    2       ; Timer HISR priority (values from
                                            ; 0 to 2, where 0 is highest)
                                            
;*****************************
;* BOARD INTERRUPT CONSTANTS *
;*****************************
INT_CNTRL_BASE_1            DCD   0x2001B800 ; Base address for interrupt handler 1
INT_CNTRL_BASE_2            DCD   0xC001B800 ; Base address for interrupt handler 2

; Interrupt Controller Registers (page 6-17, 18 of the 
; OMAP Dual Core Processor Technical Reference Manual)
INT_IRQ0_STATUS             EQU    0x30    ; (R/W)Interrupt Input Register     
INT_IRQ0_RAWSTATUS          EQU    0x18     ; (R/W)Mask Interrupt Register    
INT_IRQ0_ENABLESET	    EQU    0x00     ; (R)Source IRQ Register        
INT_IRQ0_ENABLECLR          EQU    0x0C     ; (R)Source FIQ Register    
INT_INT_SOFTSET  	    EQU    0x10     ; (R)Source IRQ Register        
INT_INT_SOFTCLEAR           EQU    0x14     ; (R)Source FIQ Register      
INT_FIQ0_STATUS             EQU    0xd4     ; (R/W)Interrupt Level Register 1
INT_FIQ0_RAWSTATUS          EQU    0xcc     ; (R/W)Interrupt Level Register 2
INT_FIQ0_ENABLESET          EQU    0xc0     ; (R/W)Interrupt Level Register 3
INT_FIQ0_ENABLECLR          EQU    0x2C     ; (R/W)Interrupt Level Register 4

INTERRUPTS_ADDR             EQU    0x00000000   ; Begining address for all handlers

; Defining vectors from ARM Peripherals Interrupt Mapping (page 6-14,15 of the 
; OMAP Dual Core Processor Technical Reference Manual)

; Level 1 Interrupt Handler
INT_IRQ0_SOFTINT            EQU    0     ; Level 2 Interrupt Handler IRQ
INT_IRQ1_UARTINT0           EQU    1     ; Camera Interrupt
INT_IRQ2_UARTINT1           EQU    2     ; RESERVED
INT_IRQ3_KBDINT             EQU    3     ; External FIQ Interrupt
INT_IRQ4_MOUSEINT           EQU    4     ; McBSP2 SPI TX Interrupt
INT_IRQ5_TIMERINT0          EQU    5     ; McBSP2 SPI RX Interrupt
INT_IRQ6_TIMERINT1          EQU    6     ; RTDX Interrupt
INT_IRQ7_TIMERINT2          EQU    7     ; DSP MMU Abort Interrupt
INT_IRQ8_RTCINT             EQU    8     ; Host Interrupt
INT_IRQ9_EXPINT0            EQU    9     ; IRQ Abort Interrupt
INT_IRQ10_EXPINT1           EQU    10    ; IRQ DSP Mailbox 1 Interrupt
INT_IRQ11_EXPINT2           EQU    11    ; IRQ DSP Mailbox 2 Interrupt
INT_IRQ12_EXPINT3           EQU    12    ; RESERVED
INT_IRQ13_PCIINT0           EQU    13    ; IRQ TIPB Bridge Private Interrupt
INT_IRQ14_PCIINT1           EQU    14    ; IRQ General Purpose I/O Interrupt
INT_IRQ15_PCIINT2           EQU    15    ; IRQ UART3 Interrupt
INT_IRQ16_PCIINT3           EQU    16    ; Timer 3 Interrupt     
INT_IRQ17_LINT              EQU    17    ; Local Bus Memory Management Unit Interrupt
INT_IRQ18_DEGINT            EQU    18    ; RESERVED
INT_IRQ19_ENUMINT           EQU    19    ; DMA Channel 0 thru Channel 6 Interrupt
INT_IRQ20_PCILBINT          EQU    20    ; DMA Channel 1 thru Channel 7 Interrupt
INT_IRQ21_EXTINT            EQU    21    ; DMA Channel 2 thru Channel 8 Interrupt


; Level 2 Interrupt Handler (under MPU Interrupt Handlers)
;INT_IRQ32_FAC               .equ    32    ; Hardware Errors
;INT_IRQ33_KEYPAD            .equ    33    ; Keypad Interrupt
;INT_IRQ34_MICROWARE_TX      .equ    34    ; Microware Tx Interrupt  
;INT_IRQ35_MICROWARE_RX      .equ    35    ; Microware Rx Interrupt  
;INT_IRQ36_I2C               .equ    36    ; I2C Interrupt  
;INT_IRQ37_MPUIO             .equ    37    ; Microprocessor Unit I/O Interrupt  
;INT_IRQ38_USB_HHC_1         .equ    38    ; USB HHC 1 Interrupt  
;INT_IRQ39_USB_HHC_2         .equ    39    ; USB HHC 2 Interrupt
;INT_IRQ40_RESERVED          .equ    40    ; Reserved
;INT_IRQ41_RESERVED          .equ    41    ; Reserved
;INT_IRQ42_McBSP3_TX         .equ    42    ; McBSP3 Transmit Interrupt  
;INT_IRQ43_McBSP3_RX         .equ    43    ; McBSP3 Receive Interrupt  
;INT_IRQ44_McBSP1_TX         .equ    44    ; McBSP1 Transmit Interrupt  
;INT_IRQ45_McBSP1_RX         .equ    45    ; McBSP1 Receive Interrupt  
;INT_IRQ46_UART1             .equ    46    ; UART 1 Interrupt (Bluetooth)  
;INT_IRQ47_UART2             .equ    47    ; UART 2 Interrupt  
;INT_IRQ48_MCSI1_FE          .equ    48    ; MCSI 1 FE Interrupt  
;INT_IRQ49_MCSI2_FE          .equ    49    ; MCSI 2 FE Interrupt
;INT_IRQ50_RESERVED          .equ    50    ; RESERVED
;INT_IRQ51_RESERVED          .equ    51    ; RESERVED
;INT_IRQ52_USB_FUN_GEN       .equ    52    ; USB Function Generator Interrupt  
;INT_IRQ53_1_WIRE            .equ    53    ; 1 Wire Interrupt