uhal.h

Nuclues嵌入式RTOS源码

/***************************************************************************
  SCDMA-SoC Driver:	uhal.h
   
****************************************************************************

  This file contains Defines, Structures, Routines used & defined in the uHAL library

	Revision : 	1.0
	Date: 		2003/07/24 
	Author: 	lilin

****************************************************************************/

#ifndef __uhal_h                /* Only include stuff once */
#define __uhal_h

#include "socPlatform.h"

/* These defines are in a common coding practices header file */
#ifndef	ERROR
#define ERROR		-1               /* -MAX_INT would be better?? (or errno.h) */
#endif
#ifndef	OK
#define OK		0                   /* Can never work out should this be 1 or 0? */
#endif
#ifndef	FALSE
#define FALSE		0
#endif

#define TRUE		1
#define FALSE		0

#define	NULL		0

#define ENABLE		1
#define DISABLE		0


/* General ERROR/SUCCESSFUL returns */
#define MSG_FAILURE                -1
#define MSG_SUCCESS                 0

#define	RESETV		0
#define	UNDV		1
#define	SWIV		2
#define	IABTV		3
#define	DABTV		4
#define	IRQV		6
#define	FIQV		7
#define MAX_VECTORS 	7


/* A function with no argument returning pointer to a void function */
typedef void (*PrVoid) (void);
typedef void (*PrHandler) (unsigned long);  /* As PrVoid with one parameter */
typedef int (*PrTest) (void);  /* As PrVoid with one parameter */

/* A function with no argument returning PrVoid */
typedef PrVoid(*PrPrVoid) (void);

struct uHALis_IRQ
{
    PrHandler 		handler;          /* Routine for specific interrupt */
    unsigned int 	flags;
    unsigned int 	mask;
    const unsigned char *name;             /* Debug, owner id */
    struct uHALis_IRQ 	*next;    /* Handy for shared interrupts */
};


/* Enum to describe timer: free, one-shot, on-going interval or locked-out */
enum uHALe_TimerState
{
    T_FREE, 
    T_ONESHOT, 
    T_INTERVAL, 
    T_MASKED,
    T_LOCKED
};

/* Define in dma.c */
/* Enum to describe DMA work mode: External Memory to LCD, External Memory to DSP memory,
				   RFIO to DSP memory, APB peripheral to DSP internal memory,
				   APB peripheral to APB peripheral, APB peripheral to external memory*/
enum uHALe_TransType
{
    NO_INIT,
    UART_MEM,		
    MEM_UART,	
    MEM_MEM		
};

enum uHALe_ChannelState
{
    CH_FREE,
    CH_DIS,
    CH_EN	
};

struct uHALis_DMA
{
    unsigned int 		channel;           /* Channel number */
    enum uHALe_TransType 	mode;		   /* Channel work mode */
    enum uHALe_ChannelState	state;		   /* Channel state */
    PrHandler 			handler;          /* User Routine */
    const unsigned char 	*name;             /* Debug, owner id */
    struct uHALis_DMA 		*next;
};

#define	ENABLE			1
#define DISABLE			0

#define MAX_DMA_CHANNEL		4
#define MAX_DMA_INTTYPE		4

/* Define in sim.c */
#define MAX_SIM_RSTTYPE		2
#define MAX_SIM_INTTYPE		9

/* Define in auxif.c */
#define MAX_AUXIF_AD_CHANNEL	3
#define MAX_AUXIF_DA_CHANNEL	1

/* Define in kbs.c */
#define MAX_KBS_INTTYPE		6
#define MAX_KBS_CNTTYPE		1

enum uHALe_KBS_mode
{
    GENERAL,
    LP,
    FORBID,
    AP
    
};

#define KBS_FAST_RSP		FALSE
#define KBS_LP_CNT_VALUE	0x8f00
#define KBS_AP_CNT_VALUE	0x8f00

/* define in MEMCTL */
#define MEM_CHIP0_EN		1
#define MEM_CHIP1_EN		1
#define MEM_CHIP2_EN		0
#define MEM_CHIP3_EN		1
#define MEM_CHIP4_EN		0
#define MEM_CHIP5_EN		0
#define MEM_CHIP6_EN		0
#define MEM_CHIP7_EN		0

/* Memory controller chip select base address */
#define CHIP0_BASEADDR		0xC200
#define CHIP1_BASEADDR		0xC400
#define CHIP2_BASEADDR		0x0000
#define CHIP3_BASEADDR		0xC800
#define CHIP4_BASEADDR		0x0000
#define CHIP5_BASEADDR		0x0000
#define CHIP6_BASEADDR		0x0000
#define CHIP7_BASEADDR		0x0000

/* Memory controller chip select register set */
#define CHIP0_REG_SELECT	0
#define CHIP1_REG_SELECT	1
#define CHIP2_REG_SELECT	0
#define CHIP3_REG_SELECT	2
#define CHIP4_REG_SELECT	0
#define CHIP5_REG_SELECT	0
#define CHIP6_REG_SELECT	0
#define CHIP7_REG_SELECT	0

/* Memory controller chip select memory type */
#define CHIP0_MEM_TYPE		2
#define CHIP1_MEM_TYPE		1
#define CHIP2_MEM_TYPE		0
#define CHIP3_MEM_TYPE		0
#define CHIP4_MEM_TYPE		0
#define CHIP5_MEM_TYPE		0
#define CHIP6_MEM_TYPE		0
#define CHIP7_MEM_TYPE		0

/* Memory controller chip select memory size */
#define CHIP0_MEM_SIZE		6
#define CHIP1_MEM_SIZE		3
#define CHIP2_MEM_SIZE		0
#define CHIP3_MEM_SIZE		8
#define CHIP4_MEM_SIZE		0
#define CHIP5_MEM_SIZE		0
#define CHIP6_MEM_SIZE		0
#define CHIP7_MEM_SIZE		0

/* Memory Controller Chip Select Alias Base Address */
#define MEM_CHIP0_ALIAS_EN	0
#define MEM_CHIP1_ALIAS_EN	0

#define MEM_CHIP0_ALIAS_BASE_ADDRESS	0x0000
#define MEM_CHIP1_ALIAS_BASE_ADDRESS	0x0000

/* Memory Controller Chip Select Remap Base Address */
#define MEM_CHIP0_REMAP_EN	0
#define MEM_CHIP1_REMAP_EN	0

#define MEM_CHIP0_REMAP_BASE_ADDRESS	0x0000
#define MEM_CHIP1_REMAP_BASE_ADDRESS	0x0000

/* SDRAM configuration Set Value */
#define MEM_SD_DATA_WIDTH	1
#define MEM_SD_COL_ADDR_WIDTH	7
#define MEM_SD_ROW_ADDR_WIDTH	10
#define MEM_SD_BANK_ADDR_WIDTH	1

/* SDRAM Timing Set Parameters */
#define MEM_SD_T_RC		6
#define MEM_SD_T_XSR		6
#define MEM_SD_T_RCAR		9
#define MEM_SD_T_WR		0
#define MEM_SD_T_RP		2
#define MEM_SD_T_RCD		0
#define MEM_SD_T_RAS_MIN	4
#define MEM_SD_CAS_LATENCY	1
#define MEM_SD_T_WTR		0
#define MEM_SD_NUM_INIT_REF	7
#define MEM_SD_T_INIT		10000

/* SDRAM Refresh period value */
#define MEM_SD_REFRESH_INTERVAL		1040

/* SDRAM Control Parameters */
#define MEM_SD_NUM_OPEN_BANKS		3
#define MEM_SD_READ_PIPE		2
#define MEM_SD_FULL_REFRESH_AFTER_SR	0
#define MEM_SD_FULL_REFRESH_BEFORE_SR	0
#define MEM_SD_PRECHARGE_ALGORITHM	1

/* Static Timing Register0 Set Value */
#define MEM_REG0_SM_READ_PIPE			0
#define MEM_REG0_SM_LOW_FREQ_SYNC_DEVICE	0
#define MEM_REG0_SM_READY_MODE			0
#define MEM_REG0_SM_PAGE_SIZE			0
#define MEM_REG0_SM_PAGE_MODE			1
#define MEM_REG0_SM_T_PRC			2
#define MEM_REG0_SM_T_BTA			1
#define MEM_REG0_SM_T_WP			3
#define MEM_REG0_SM_T_WR			1
#define MEM_REG0_SM_T_AS			1
#define MEM_REG0_SM_T_RC			6

#define MEM_REG1_SM_READ_PIPE			0
#define MEM_REG1_SM_LOW_FREQ_SYNC_DEVICE	0
#define MEM_REG1_SM_READY_MODE			0
#define MEM_REG1_SM_PAGE_SIZE			0
#define MEM_REG1_SM_PAGE_MODE			0
#define MEM_REG1_SM_T_PRC			15
#define MEM_REG1_SM_T_BTA			3
#define MEM_REG1_SM_T_WP			5
#define MEM_REG1_SM_T_WR			1
#define MEM_REG1_SM_T_AS			1
#define MEM_REG1_SM_T_RC			6

#define MEM_REG2_SM_READ_PIPE			3
#define MEM_REG2_SM_LOW_FREQ_SYNC_DEVICE	0
#define MEM_REG2_SM_READY_MODE			0
#define MEM_REG2_SM_PAGE_SIZE			0
#define MEM_REG2_SM_PAGE_MODE			1
#define MEM_REG2_SM_T_PRC			2
#define MEM_REG2_SM_T_BTA			4
#define MEM_REG2_SM_T_WP			3
#define MEM_REG2_SM_T_WR			1
#define MEM_REG2_SM_T_AS			1
#define MEM_REG2_SM_T_RC			6

/* FLASH reset/power-down high to read/write delay */
#define MEM_T_RPD		200

#define MEM_REG0_SM_DATA_WIDTH		0
#define MEM_REG1_SM_DATA_WIDTH		0
#define MEM_REG2_SM_DATA_WIDTH		1

/* Define in PWM */
#define MAX_PWM_CNTLTYPE		17

/* Define Queue Struct */
typedef struct queue_Message
{
    unsigned char 	id;
    unsigned char 	msg1;
    unsigned char 	msg2;
    unsigned char 	msg3;
    unsigned char 	msg4;
    unsigned char 	msg5;
    unsigned char 	msg6;
    unsigned char 	msg7;
};

/* Define Debug Struct */
typedef struct debug_Message
{
    unsigned char 	id;	//0: printf
    unsigned char 	task;	//which task send it
    unsigned char 	*ps;	//pointer to printf buffer
    
};