📄 public.h
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;/***********************************************************************
; Copyright ARM Limited 1998 - 2000. All rights reserved.
;************************************************************************
;
; Integrator address map
;
; NOTE: This is a multi-hosted header file for use with uHAL and
; supported debuggers.
;
; $Id: platform.s,v 1.48 2002/01/21 16:58:56 asims Exp $
;
;***********************************************************************/
#ifndef __public_h
#define __public_h
/* These defines are in a common coding practices header file */
#ifndef ERROR
#define ERROR -1 /* -MAX_INT would be better?? (or errno.h) */
#endif
#ifndef OK
#define OK 0 /* Can never work out should this be 1 or 0? */
#endif
#ifndef FALSE
#define FALSE 0
#endif
#define TRUE 1
#define FALSE 0
#define NULL 0
#define ENABLE 1
#define DISABLE 0
#define MUXBase 0x2001ED00
#define PINENBase 0x2001ED04
/*****************************************************************************/
/* MUX register bit */
/*****************************************************************************/
#define MUX ((volatile unsigned *)MUXBase)
#define MUX_ETM_TRACE_SYNC_GPIO2_15 31
#define MUX_ETM_PIPESTATE2_GPIO2_14 30
#define MUX_ETM_PIPESTATE1_GPIO2_13 29
#define MUX_ETM_PIPESTATE0_GPIO2_12 28
#define MUX_SSI2_TXD_GPIO2_11 27
#define MUX_SSI2_RXD_GPIO2_10 26
#define MUX_SSI2_SSN_GPIO2_9 25
#define MUX_SSI2_SCLK_GPIO2_8 24
#define MUX_SSI2_TXD_GPIO2_7 23
#define MUX_SSI2_RXD_GPIO2_6 22
#define MUX_SSI2_SSN_GPIO2_5 21
#define MUX_SSI2_SCLK_GPIO2_4 20
#define MUX_UART3_CTS_GPIO2_3 19
#define MUX_UART3_RTS_GPIO2_2 18
#define MUX_UART3_TXD_GPIO2_1 17
#define MUX_UART3_RXD_GPIO2_0 16
#define MUX_AUX0N3_GPIO1_15 15
#define MUX_AUXON2_GPIO1_14 14
#define MUX_CLKOUT_GPIO1_13 13
#define MUX_EXTAL_IN_GPIO1_12 12
#define MUX_UART1_SIROUT_GPIO1_11 11
#define MUX_UART1_SIRIN_GPIO1_10 10
#define MUX_UART_RTS_GPIO1_9 9
#define MUX_UART_CTS_GPIO1_8 8
#define MUX_UART1_TXD_GPIO1_7 7
#define MUX_UART1_RXD_GPIO1_6 6
#define MUX_PWMO1_GPIO1_5 5
#define MUX_PWMO0_GPIO1_4 4
#define MUX_SIM_VCEN_GPIO1_3 3
#define MUX_SIM_RST_GPIO1_2 2
#define MUX_SIM_IO_GPIO1_1 1
#define MUX_SIM_CLK_GPIO1_0 0
/*****************************************************************************/
/* PINEN register bit */
/*****************************************************************************/
#define PINEN ((volatile unsigned *)PINENBase)
#define PINEN_CS7_EXTR_INT_2 21
#define PINEN_CS6_EXTR_INT_1 20
#define PINEN_CS5_EXTR_INT_0 19
#define PINEN_ETM 18
#define PINEN_RFDA_ETM_Z 17
#define PINEN_RFBP_Z 16
#define PINEN_RFCTRL_Z 15
#define PINEN_AUX_ON3_Z 14
#define PINEN_AUX_ON2_Z 13
#define PINEN_CLKOUT_Z 12
#define PINEN_MEMCLKOUT_Z 11
#define PINEN_SDRAM_Z 10
#define PINEN_CS2_Z 9
#define PINEN_LCD_Z 8
#define PINEN_SSI2_Z 7
#define PINEN_SSI1_Z 6
#define PINEN_UART3_Z 5
#define PINEN_UART2_Z 4
#define PINEN_UART1_Z 3
#define PINEN_PWM1_Z 2
#define PINEN_PWM0_Z 1
#define PINEN_SIM_Z 0
/*****************************************************************************/
/* Definitions of IRQ and FIQ ids for Logic Tile */
/*****************************************************************************/
#define ICTL_IRQ_EXTINT0 0
#define ICTL_IRQ_TIMERINT2 1
#define ICTL_IRQ_TIMERINT0 2
#define ICTL_IRQ_UARTINT1 3
#define ICTL_IRQ_PWMINT 4
#define ICTL_IRQ_SIMINT 5
#define ICTL_IRQ_KBSINT 6
#define ICTL_IRQ_LCDINT 7
#define ICTL_IRQ_UARTINT2 8
#define ICTL_IRQ_TIMERINT1 9
#define ICTL_IRQ_AUXIFINT 10
#define ICTL_IRQ_RTCINT 11
#define ICTL_IRQ_DMAINT 12
#define ICTL_IRQ_GPIOINT1 13
#define ICTL_IRQ_EXTINT1 14
#define ICTL_IRQ_TIMERINT3 15
#define ICTL_IRQ_WDTINT 16
#define ICTL_IRQ_CPRINT 17
#define ICTL_IRQ_SSIINT1 18
#define ICTL_IRQ_SSIINT2 19
#define ICTL_IRQ_GPIOINT2 20
#define ICTL_IRQ_UARTINT0 21
/*****************************************************************************/
/* function define */
/*****************************************************************************/
#endif
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