socplatform.h

Nuclues嵌入式RTOS源码

/* MEMC_CSREMAP0,1 */
#define CHIP_SELECT_REMAP_ADDRESS	15

/* MEMC_SMTMGR_SET0,1,2 */
#define B_SM_READ_PIPE			28
#define B_SM_LOW_FREQ_SYNC_DEVICE	27
#define B_SM_READY_MODE			26
#define B_SM_PAGE_SIZE			24
#define B_SM_PAGE_MODE			23
#define B_SM_T_PRC			19
#define B_SM_T_BTA			16
#define B_SM_T_WP			10
#define B_SM_T_WR			8
#define B_SM_T_AS			6
#define B_SM_T_RC			0

/* MEMC_SMCTLR */
#define SM_DATA_WIDTH_SET2	13
#define SM_DATA_WIDTH_SET1	10
#define SM_DATA_WIDTH_SET0	7
#define SM_WP_N_SET2		3
#define SM_WP_N_SET1		2
#define SM_WP_N_SET0		1
#define SM_RP_N			0

/* MEMC_FLASH_OPCODE */
#define FLASH_OPERATION		12
#define FLASH_OPCODE		0

/* MEMC_ETN_MODE_REG */
#define OPERATION_MODE		3
#define QFC			2
#define DRIVE_STRENGTH		1
#define DLL			0

/* Static memory data bus */
#define SM_DATA_WIDTH_16	0
#define SM_DATA_WIDTH_32	1
#define SM_DATA_WIDTH_64	2
#define SM_DATA_WIDTH_128	3
#define SM_DATA_WIDTH_8		4

/* register select */
#define REG_SET0		0
#define REG_SET1		1
#define REG_SET2		2

/* memory type */
#define MEM_SDRAM		0
#define MEM_SRAM		1
#define MEM_FLASH		2
#define	MEM_ROM			3

/* memory size */
#define MEM_64KB		1
#define MEM_128KB		2
#define MEM_256KB		3
#define MEM_512KB		4
#define MEM_1MB			5
#define MEM_2MB			6
#define MEM_4MB			7
#define MEM_8MB			8
#define MEM_16MB		9
#define MEM_32MB		10
#define MEM_64MB		11
#define MEM_128MB		12
#define MEM_256MB		13
#define MEM_512MB		14
#define MEM_1GB			15
#define MEM_2GB			16
#define MEM_4GB			17

/* Memory Chip Number */
#define MEM_CHIP0		0
#define MEM_CHIP1		1
#define MEM_CHIP2		2
#define MEM_CHIP3		3
#define MEM_CHIP4		4
#define MEM_CHIP5		5
#define MEM_CHIP6		6
#define MEM_CHIP7		7

/* Static Timing Register Set Type */
#define SM_READ_PIPE		0
#define SM_LOW_FREQ_SYNC_DEVICE	1
#define SM_READY_MODE		2
#define SM_PAGE_SIZE		3
#define SM_PAGE_MODE		4
#define SM_T_PRC		5
#define SM_T_BTA		6
#define SM_T_WP			7
#define SM_T_WR			8
#define SM_T_AS			9
#define SM_T_RC			10
#define SM_DATA_WIDTH		11

/* SDRAM configuration Set Type */
#define SD_DATA_WIDTH		0
#define SD_COL_ADDR_WIDTH	1
#define SD_ROW_ADDR_WIDTH	2
#define SD_BANK_ADDR_WIDTH	3

/* SDRAM timing set type */
#define SD_T_RC			0
#define SD_T_XSR		1
#define SD_T_RCAR		2
#define SD_T_WR			3
#define SD_T_RP			4
#define SD_T_RCD		5
#define SD_T_RAS_MIN		6
#define SD_CAS_LATENCY		7
#define SD_T_WTR		8
#define SD_NUM_INIT_REF		9
#define SD_T_INIT		10

/* SDRAM control set type */
#define SD_NUM_OPEN_BANKS		0
#define SD_READ_PIPE			1
#define SD_FULL_REFRESH_AFTER_SR	2
#define SD_FULL_REFRESH_BEFORE_SR	3
#define SD_PRECHARGE_ALGORITHM		4
#define SD_REFRESH_INTERVAL		5

/*****************************************************************************/
/* UART register for DTT6C01A0410                    	                     */
/*****************************************************************************/
#define	UART2_RBR		((volatile unsigned char*)UART2Base)
#define	UART2_THR		((volatile unsigned char*)UART2Base)
#define	UART2_DLL		((volatile unsigned *)UART2Base)
#define	UART2_IER		((volatile unsigned *)(UART2Base + 0x004))
#define	UART2_DLH		((volatile unsigned *)(UART2Base + 0x004))
#define	UART2_IIR		((volatile unsigned *)(UART2Base + 0x008))
#define	UART2_FCR		((volatile unsigned *)(UART2Base + 0x008))
#define	UART2_LCR		((volatile unsigned *)(UART2Base + 0x00C))
#define	UART2_MCR		((volatile unsigned *)(UART2Base + 0x010))
#define	UART2_LSR		((volatile unsigned *)(UART2Base + 0x014))
#define	UART2_MSR		((volatile unsigned *)(UART2Base + 0x018))
#define	UART2_SCR		((volatile unsigned *)(UART2Base + 0x01c))

#define	UART1_RBR_THR		((volatile unsigned *)UART1Base)
#define	UART1_IER		((volatile unsigned *)(UART1Base + 0x004))
#define	UART1_IIR_FCR		((volatile unsigned *)(UART1Base + 0x008))
#define	UART1_LCR		((volatile unsigned *)(UART1Base + 0x00C))
#define	UART1_MCR		((volatile unsigned *)(UART1Base + 0x010))
#define	UART1_LSR		((volatile unsigned *)(UART1Base + 0x014))
#define	UART1_MSR		((volatile unsigned *)(UART1Base + 0x018))
#define	UART1_SCR		((volatile unsigned *)(UART1Base + 0x01c))

/*****************************************************************************/
/* Definition for UART Controller                 			     */
/*****************************************************************************/
#define UART_IER_ERBFI		0
#define UART_IER_ETBEI		1
#define UART_IER_ELSI		2
#define UART_IER_EDSSI		3
#define UART_IER_PTIME		7

#define UART_IIR_FIFO		6
#define UART_IIR_MSC		0x00
#define UART_IIR_THRE		0x02
#define UART_IIR_RDA		0x04
#define UART_IIR_RS		0x06
#define UART_IIR_CTO		0x0C

#define UART_FCR_FIFO_EN		0
#define UART_FCR_RCVR_FIFO_RESET	1
#define UART_FCR_XMIT_FIFO_RESET	2
#define UART_FCR_DMA_MODE		3
#define UART_FCR_TX_EMPTY		0x30
#define UART_FCR_RCVR_FULL		0xC0

#define UART_LCR_CLS		0x03
#define UART_LCR_STOP		2
#define UART_LCR_PEN		3
#define UART_LCR_EPS		4
#define UART_LCR_PARITY		5
#define UART_LCR_BREAK		6
#define UART_LCR_DLAB		7

#define UART_MCR_DTR		0
#define UART_MCR_RTS		1
#define UART_MCR_OUT1		2
#define UART_MCR_OUT2		3
#define UART_MCR_LOOPBACK	4
#define UART_MCR_AFCE		5
#define UART_MCR_SIRE		6

#define UART_LSR_DR			0
#define UART_LSR_OE			1
#define UART_LSR_PE			2
#define UART_LSR_FE			3
#define UART_LSR_BI			4
#define UART_LSR_THRE			5
#define UART_LSR_TEMT			6
#define UART_LSR_RXFIFO_ERROR		7

#define UART_MSR_DCTS			0
#define UART_MSR_DDSR			1
#define UART_MSR_TERI			2
#define UART_MSR_DDCD			3
#define UART_MSR_CTS			4
#define UART_MSR_DSR			5
#define UART_MSR_RI			6
#define UART_MSR_DCD			7

/*****************************************************************************/
/* PWM register for DTT6C01A0410                    	                     */
/*****************************************************************************/
#define	PWM0_CNTL		((volatile unsigned *)PWMBase)
#define	PWM0_COUNT		((volatile unsigned *)(PWMBase + 0x004))
#define	PWM0_PERIOD		((volatile unsigned *)(PWMBase + 0x008))
#define PWM0_FIFO		((volatile unsigned *)(PWMBase + 0x00c))
#define PWM0_SAMPLE		((volatile unsigned *)(PWMBase + 0x00c))
#define	PWM1_CNTL		((volatile unsigned *)(PWMBase + 0x010))
#define	PWM1_COUNT		((volatile unsigned *)(PWMBase + 0x014))
#define	PWM1_PERIOD		((volatile unsigned *)(PWMBase + 0x018))
#define PWM1_FIFO		((volatile unsigned *)(PWMBase + 0x01c))
#define PWM1_SAMPLE		((volatile unsigned *)(PWMBase + 0x01c))

/*****************************************************************************/
/* Definition for PWM Controller                 			     */
/*****************************************************************************/

#define PWM_CNTL_MODE		17
#define PWM_CNTL_SWR		16
#define PWM_CNTL_CLKSRC		15
#define PWM_CNTL_PRS		8
#define PWM_CNTL_IRQ		7
#define PWM_CNTL_IRQEN		6
#define PWM_CNTL_FIFOAV		5
#define PWM_CNTL_EN		4
#define PWM_CNTL_CLKSEL		0

#define PWM0			0
#define PWM1			1

#define PWM_MODE0		0
#define PWM_MODE1		1


/*****************************************************************************/
/* LCDC register for DTT6C01A0410                    	                     */
/*****************************************************************************/
#define	LCDC_BY_CNTL		((volatile unsigned *)(LCDCBase + 0x338))
#define	LCDC_BY_IOUT		((volatile unsigned *)(LCDCBase + 0x33c))
#define	LCDC_BY_DOUT		((volatile unsigned *)(LCDCBase + 0x340))
#define LCDC_BY_BITSEL		((volatile unsigned *)(LCDCBase + 0x344))

/*****************************************************************************/
/* Definition for LCD Controller                 			     */
/*****************************************************************************/
#define LCDC_CNTL_BY_EN		0
#define LCDC_CNTL_RW_BP		1
#define LCDC_CNTL_RW_FP		8
#define LCDC_CNTL_TAH		15
#define LCDC_CNTL_TAS		22
#define LCDC_CNTL_INTM		29
#define LCDC_CNTL_BUF_FLUSH	30
#define LCDC_CNTL_SUB_PANEL	31

#define LCDC_32BIT		0
#define LCDC_16BIT		1


/*****************************************************************************/
/* DPRAM register for DTT6C01A0410                    	                     */
/*****************************************************************************/
#define DPRAM_BANK0		((volatile unsigned *)(DPRAMBase))
#define DPRAM_BANK1		((volatile unsigned *)(DPRAMBase + 0x0100))
#define DPRAM_BANK2		((volatile unsigned *)(DPRAMBase + 0x0200))
#define DPRAM_BANK3		((volatile unsigned *)(DPRAMBase + 0x0300))
#define	DPRAM_ARM_INT_REQ	((volatile unsigned *)(DPRAMBase + 0x1000))
#define	DPRAM_DSP_INT_STATUS	((volatile unsigned *)(DPRAMBase + 0x1004))
#define	DPRAM_DSP_INTCLR	((volatile unsigned *)(DPRAMBase + 0x1008))
#define	DPRAM_ARM_STATUS	((volatile unsigned *)(DPRAMBase + 0x100C))
#define	DPRAM_DSP_STATUS	((volatile unsigned *)(DPRAMBase + 0x1010))

#define DPRAM2_BANK0		((volatile unsigned *)(DPRAM2Base)
#define DPRAM2_BANK1		((volatile unsigned *)(DPRAM2Base + 0x0100))
#define DPRAM2_BANK2		((volatile unsigned *)(DPRAM2Base + 0x0200))
#define DPRAM2_BANK3		((volatile unsigned *)(DPRAM2Base + 0x0300))
#define	DPRAM2_DSP_INT_REQ	((volatile unsigned *)(DPRAM2Base + 0x1000))
#define	DPRAM2_ARM_INT_STATUS	((volatile unsigned *)(DPRAM2Base + 0x1004))
#define	DPRAM2_ARM_INTCLR	((volatile unsigned *)(DPRAM2Base + 0x1008))
#define	DPRAM2_DSP_STATUS	((volatile unsigned *)(DPRAM2Base + 0x100C))
#define	DPRAM2_ARM_STATUS	((volatile unsigned *)(DPRAM2Base + 0x1010))

/*****************************************************************************/
/* RTC register for DTT6C01A0410                    	                     */
/*****************************************************************************/
#define	RTC_CCVR		((volatile unsigned *)RTCBase)
#define	RTC_CMR			((volatile unsigned *)(RTCBase + 0x04))
#define	RTC_CLR			((volatile unsigned *)(RTCBase + 0x08))
#define	RTC_CCR			((volatile unsigned *)(RTCBase + 0x0C))
#define	RTC_STAT		((volatile unsigned *)(RTCBase + 0x10))
#define	RTC_RSTAT		((volatile unsigned *)(RTCBase + 0x14))
#define	RTC_EOI			((volatile unsigned *)(RTCBase + 0x18))

/*****************************************************************************/
/* Definition for RTC Controller                 			     */
/*****************************************************************************/
#define RTC_CCR_WEN		3
#define RTC_CCR_EN		2
#define RTC_CCR_MASK		1
#define RTC_CCR_IEN		0

/*****************************************************************************/
/* GPIO1 register for DTT6C01A0410                    	                     */
/*****************************************************************************/
#define	GPIO1_DR		((volatile unsigned *)(GPIO1Base + 0x00))
#define	GPIO1_DDR		((volatile unsigned *)(GPIO1Base + 0x04))
#define	GPIO1_INTEN		((volatile unsigned *)(GPIO1Base + 0x30))
#define GPIO1_INTMASK		((volatile unsigned *)(GPIO1Base + 0x34))
#define GPIO1_INT_LEVEL		((volatile unsigned *)(GPIO1Base + 0x38))
#define GPIO1_INT_POLARITY	((volatile unsigned *)(GPIO1Base + 0x3C))
#define GPIO1_INTSTATUS		((volatile unsigned *)(GPIO1Base + 0x40))
#define GPIO1_RAWINTSTATUS	((volatile unsigned *)(GPIO1Base + 0x44))
#define GPIO1_INT_DEBOUNCE	((volatile unsigned *)(GPIO1Base + 0x48))
#define GPIO1_INT_EOI		((volatile unsigned *)(GPIO1Base + 0x4C))
#define GPIO1_EXT_PORT		((volatile unsigned *)(GPIO1Base + 0x50))
#define GPIO1_LS_SYNC		((volatile unsigned *)(GPIO1Base + 0x60))

#define GPIO1_MULTIPLE		((volatile unsigned *)(0x2001ED00))   

/*****************************************************************************/
/* WDT register for DTT6C01A0410                     	                     */
/*****************************************************************************/
#define	WDT1_CR			((volatile unsigned *)(WDT1Base + 0x00))
#define	WDT1_TORR		((volatile unsigned *)(WDT1Base + 0x04))
#define	WDT1_CCVR		((volatile unsigned *)(WDT1Base + 0x08))
#define WDT1_CRR		((volatile unsigned *)(WDT1Base + 0x0c))
#define WDT1_STAT		((volatile unsigned *)(WDT1Base + 0x10))
#define WDT1_EOI		((volatile unsigned *)(WDT1Base + 0x14))
#define WDT1_VID		((volatile unsigned *)(WDT1Base + 0x18))

/*****************************************************************************/
/* Definition for WDT Controller                 			     */
/*****************************************************************************/
#define WDT_CR_RPL		2
#define WDT_CR_RMOD		1
#define WDT_CR_WDT_EN		0
#define WDT_TORR_TOP_INIT	4
#define WDT_TORR_TOP		0
#define WDT_CRR_RESTART		0x76
#define WDT_STAT_INT		0




#define	MEM_BANK0			((volatile unsigned *)MEMBase)
#define	MEM_BANK1			((volatile unsigned *)(MEMBase + 0x100))
#define	MEM_BANK2			((volatile unsigned *)(MEMBase + 0x200))
#define	MEM_BANK3			((volatile unsigned *)(MEMBase + 0x300))

#define MEM_LINK			((volatile unsigned *)(MEMBase + 0xF00))


/*****************************************************************************/
/* System information address                 			    	     */
/*****************************************************************************/
#define SystemBase		0x800

#define	SYS_TICK		((volatile unsigned *)(SystemBase + 0x00))
#define	SYS_IDLE		((volatile unsigned *)(SystemBase + 0x04))
#define	SYS_TASK_HISR		((volatile unsigned *)(SystemBase + 0x08))
#define	SYS_TASK0		((volatile unsigned *)(SystemBase + 0x0C))
#define	SYS_TASK1		((volatile unsigned *)(SystemBase + 0x10))
#define	SYS_TASK2		((volatile unsigned *)(SystemBase + 0x14))
#define	SYS_TASK3		((volatile unsigned *)(SystemBase + 0x18))
#define	SYS_TASK4		((volatile unsigned *)(SystemBase + 0x1C))
#define	SYS_TASK5		((volatile unsigned *)(SystemBase + 0x20))