📄 socplatform.h
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#define DMA_MASK_ERR ((volatile unsigned *)(DMABase + 0x330))
#define DMA_CLR_TRF ((volatile unsigned *)(DMABase + 0x338))
#define DMA_CLR_BLOCK ((volatile unsigned *)(DMABase + 0x340))
#define DMA_CLR_SRCTRAN ((volatile unsigned *)(DMABase + 0x348))
#define DMA_CLR_DSTTRAN ((volatile unsigned *)(DMABase + 0x350))
#define DMA_CLR_ERR ((volatile unsigned *)(DMABase + 0x358))
#define DMA_STATUS_INT ((volatile unsigned *)(DMABase + 0x360))
#define DMA_REQ_SRC ((volatile unsigned *)(DMABase + 0x368))
#define DMA_REQ_DST ((volatile unsigned *)(DMABase + 0x370))
#define DMA_SGL_REQ_SRC ((volatile unsigned *)(DMABase + 0x378))
#define DMA_SGL_REQ_DST ((volatile unsigned *)(DMABase + 0x380))
#define DMA_LST_SRC ((volatile unsigned *)(DMABase + 0x388))
#define DMA_LST_DST ((volatile unsigned *)(DMABase + 0x390))
#define DMA_CFG ((volatile unsigned *)(DMABase + 0x398))
#define DMA_CH_EN ((volatile unsigned *)(DMABase + 0x3a0))
#define DMA_ID ((volatile unsigned *)(DMABase + 0x3a8))
#define DMA_TEST ((volatile unsigned *)(DMABase + 0x3b0))
#define DMA_VERSION ((volatile unsigned *)(DMABase + 0x3b8))
/*****************************************************************************/
/* Definition for DMA Controller */
/*****************************************************************************/
#define DMA_CH0 0
#define DMA_CH1 1
#define DMA_CH2 2
#define DMA_CH3 3
#define DMA_CH4 4
#define DMA_CH0_WE 8
#define DMA_CH1_WE 9
#define DMA_CH2_WE 10
#define DMA_CH3_WE 11
#define DMA_CH4_WE 12
#define CTL_INT_EN 0
#define CTL_DST_TR_WIDTH 1
#define CTL_SRC_TR_WIDTH 4
#define CTL_DINC 7
#define CTL_SINC 9
#define CTL_DEST_MSIZE 11
#define CTL_SRC_MSIZE 14
#define CTL_TT_FC 20
#define CTL_DMS 23
#define CTL_SMS 25
#define CTL_LLP_DST_EN 27
#define CTL_LLP_SRC_EN 28
#define CTL_BLOCK_TS 0
#define CTL_DONE 12
#define CFG_CH_PRIOR 5
#define CFG_CH_SUSP 8
#define CFG_FIFO_EMPTY 9
#define CFG_HS_SEL_DST 10
#define CFG_HS_SEL_SRC 11
#define CFG_RELOAD_SRC 30
#define CFG_RELOAD_DST 31
#define LLR_LMS 0
#define LLR_LOC 2
#define TRF_INT 0
#define BLOCK_INT 1
#define SRCT_INT 2
#define DSTT_INT 3
#define ERR_INT 4
#define DMA_SRC 0
#define DMA_DEST 1
#define AHB_MASTER_1 0
#define AHB_MASTER_2 1
#define DMA_MSIZE_0 0
#define DMA_MSIZE_4 1
#define DMA_MSIZE_8 2
#define DMA_MSIZE_16 3
#define DMA_MSIZE_32 4
#define DMA_MSIZE_64 5
#define DMA_MSIZE_128 6
#define DMA_MSIZE_256 7
#define DMA_ADDR_INC 0
#define DMA_ADDR_DEC 1
#define DMA_ADDR_NOCHANGE 2
#define DMA_SOFTWARE 1
#define DMA_HANDWARE 0
#define DMA_M_M 0
#define DMA_M_P 1
#define DMA_P_M 2
#define DMA_P_P 3
#define DMA_ENABLE 1
#define DMA_DISABLE 0
/*****************************************************************************/
/* SIM Controller register for DTT6C01A0410 */
/*****************************************************************************/
#define SIM_PORT_CNTL ((volatile unsigned *)SIMBase)
#define SIM_CNTL ((volatile unsigned *)(SIMBase + 0x04))
#define SIM_ENABLE ((volatile unsigned *)(SIMBase + 0x0C))
#define SIM_XMT_STATUS ((volatile unsigned *)(SIMBase + 0x10))
#define SIM_RCV_STATUS ((volatile unsigned *)(SIMBase + 0x14))
#define SIM_INT_MASK ((volatile unsigned *)(SIMBase + 0x18))
#define SIM_XMT_BUF ((volatile unsigned *)(SIMBase + 0x1C))
#define SIM_RCV_BUF ((volatile unsigned *)(SIMBase + 0x20))
#define SIM_THRESHOLD ((volatile unsigned *)(SIMBase + 0x24))
#define SIM_GUARD ((volatile unsigned *)(SIMBase + 0x28))
#define SIM_RESET ((volatile unsigned *)(SIMBase + 0x2C))
#define SIM_WAIT ((volatile unsigned *)(SIMBase + 0x30))
#define SIM_GPCNT ((volatile unsigned *)(SIMBase + 0x34))
#define SIM_DIVISOR ((volatile unsigned *)(SIMBase + 0x38))
#define SIM_PIN_MUX ((volatile unsigned *)(SIMBase + 0x100))
#define SIM_PIN_EN_CTRL ((volatile unsigned *)(SIMBase + 0x104))
/*****************************************************************************/
/* Definition for SIM Controller */
/*****************************************************************************/
#define SIM_SIM 2
#define SIM_XMT 1
#define SIM_RCV 0
#define SIM_RDRF_INT 0
#define SIM_TC_INT 1
#define SIM_OEF_INT 2
#define SIM_TFE_INT 3
#define SIM_XTE_INT 4
#define SIM_TFO_INT 5
#define SIM_TDTF_INT 6
#define SIM_GPCNT_INT 7
#define SIM_CWT_INT 8
#define SIM_RFD_INT 9
#define SIM_PCTL_SAPD 0
#define SIM_PCTL_SVEN 1
#define SIM_PCTL_SRST 2
#define SIM_PCTL_SCEN 3
#define SIM_PCTL_SCSP 4
#define SIM_CTL_IC 0
#define SIM_CTL_ICM 1
#define SIM_CTL_ANACK 2
#define SIM_CTL_ONACK 3
#define SIM_CTL_BAUD 4
#define SIM_CTL_CWTEN 7
#define SIM_CTL_GPEN 8
#define SIM_BAUD_372 0
#define SIM_BAUD_256 1
#define SIM_BAUD_128 2
#define SIM_BAUD_64 3
#define SIM_BAUD_32 4
//#define SIM_BAUD_32 5 //KEVIN modified0826
#define SIM_BAUD_16 6
#define SIM_BAUD_reg 7
#define SIM_GUARD_RCVR11 8
#define SIM_GUARD_GETU 0
/*****************************************************************************/
/* AUX IF Controller register for DTT6C01A0410 */
/*****************************************************************************/
#define AUX_AD_DATA ((volatile unsigned *)AUXIFBase)
#define AUX_DA_DATA ((volatile unsigned *)(AUXIFBase + 0x04))
#define AUX_AD_CNTL ((volatile unsigned *)(AUXIFBase + 0x08))
#define AUX_DA_CNTL ((volatile unsigned *)(AUXIFBase + 0x0c))
#define AUX_INT_MASK ((volatile unsigned *)(AUXIFBase + 0x10))
#define AUX_INT_CLR ((volatile unsigned *)(AUXIFBase + 0x14))
/*****************************************************************************/
/* Definition for AUX IF Controller */
/*****************************************************************************/
#define AD_CNTL_PD 0
#define AD_CNTL_RST 1
#define AD_CNTL_SEL 2
#define DA_CNTL_PD1 0
#define DA_CNTL_PD2 1
#define AD_CH0 0
#define AD_CH1 1
#define AD_CH2 2
#define AD_CH3 3
#define AD_INT 0
#define DA_INT 1
/*****************************************************************************/
/* KBS Controller register for DTT6C01A0410 */
/*****************************************************************************/
#define KBS_CNTL ((volatile unsigned *)KBSBase)
#define KBS_STATUS ((volatile unsigned *)(KBSBase + 0x04))
#define KBS_CODE ((volatile unsigned *)(KBSBase + 0x08))
#define KBS_COUNT ((volatile unsigned *)(KBSBase + 0x0C))
#define KBS_BUFFER ((volatile unsigned *)(KBSBase + 0x10))
#define KBS_INTCLR ((volatile unsigned *)(KBSBase + 0x14))
/*****************************************************************************/
/* Definition for KBS Controller */
/*****************************************************************************/
#define KBS_CNTL_MODE 25
#define KBS_CNTL_CLR 24
#define KBS_CNTL_RESET 23
#define KBS_CNTL_CLKSRC 22
//#define KBS_CNTL_PRESCALER 13
#define KBS_KOV_INTMASK 19
#define KBS_FIFOFUL_INTMASK 18
#define KBS_ERR_INTMASK 17
#define KBS_LC_INTMASK 16
#define KBS_RC_INTMASK 15
#define KBS_KR_INTMASK 14
#define KBS_KP_INTMASK 13
#define KBS_CNTL_INTEN 12
#define KBS_KP_INTEN 11
#define KBS_KR_INTEN 10
#define KBS_ERR_INTEN 9
#define KBS_FIFOFUL_INTEN 8
#define KBS_KOV_INTEN 7
#define KBS_LC_INTEN 6
#define KBS_RC_INTEN 5
#define KBS_CNTL_RLSMODE 4
#define KBS_CNTL_LOOPS 3
#define KBS_CNTL_FKSCLK 2
#define KBS_CNTL_SKSCLK 0
#define KBS_KP_INT 0
#define KBS_KR_INT 1
#define KBS_RC_INT 2
#define KBS_LC_INT 3
#define KBS_ERR_INT 4
#define KBS_FIFOFUL_INT 5
#define KBS_KOV_INT 6
#define KBS_FIFO_STATE 7
#define KBS_WMODE 8
#define KBS_BUFEN 10
#define KBS_BUF 11
#define KBS_RC_CNT 0
#define KBS_LC_CNT 1
#define KBS_SYS_CLK 0
#define KBS_CLK32 1
#define KBS_RLS_NOWAIT 0
#define KBS_RLS_WAIT 1
#define KBS_LOOPS_3 0
#define KBS_LOOPS_4 1
#define KBS_FKSCLK_16 0
#define KBS_FKSCLK_8 1
#define KBS_SKSCLK_16 00
#define KBS_SKSCLK_32 01
#define KBS_SKSCLK_64 10
#define KBS_SKSCLK_128 11
#define KBS_MODE_GENERAL 00
#define KBS_MODE_LP 01
#define KBS_MODE_FORBID 10
#define KBS_MODE_AP 11
#define KBS_CODE_KEY 0
#define KBS_BUF_KEY 1
/*****************************************************************************/
/* MEMCTL register for DTT6C01A0410 */
/*****************************************************************************/
#define MEMC_SCONR ((volatile unsigned *)MEMCTLBase)
#define MEMC_STMGR0 ((volatile unsigned *)(MEMCTLBase + 0x04))
#define MEMC_STMGR1 ((volatile unsigned *)(MEMCTLBase + 0x08))
#define MEMC_SCTLR ((volatile unsigned *)(MEMCTLBase + 0x0c))
#define MEMC_SREFR ((volatile unsigned *)(MEMCTLBase + 0x10))
#define MEMC_SCSLR0 ((volatile unsigned *)(MEMCTLBase + 0x14))
#define MEMC_SCSLR1 ((volatile unsigned *)(MEMCTLBase + 0x18))
#define MEMC_SCSLR2 ((volatile unsigned *)(MEMCTLBase + 0x1c))
#define MEMC_SCSLR3 ((volatile unsigned *)(MEMCTLBase + 0x20))
#define MEMC_SCSLR4 ((volatile unsigned *)(MEMCTLBase + 0x24))
#define MEMC_SCSLR5 ((volatile unsigned *)(MEMCTLBase + 0x28))
#define MEMC_SCSLR6 ((volatile unsigned *)(MEMCTLBase + 0x2c))
#define MEMC_SCSLR7 ((volatile unsigned *)(MEMCTLBase + 0x30))
#define MEMC_SMSKR0 ((volatile unsigned *)(MEMCTLBase + 0x54))
#define MEMC_SMSKR1 ((volatile unsigned *)(MEMCTLBase + 0x58))
#define MEMC_SMSKR2 ((volatile unsigned *)(MEMCTLBase + 0x5c))
#define MEMC_SMSKR3 ((volatile unsigned *)(MEMCTLBase + 0x60))
#define MEMC_SMSKR4 ((volatile unsigned *)(MEMCTLBase + 0x64))
#define MEMC_SMSKR5 ((volatile unsigned *)(MEMCTLBase + 0x68))
#define MEMC_SMSKR6 ((volatile unsigned *)(MEMCTLBase + 0x6c))
#define MEMC_SMSKR7 ((volatile unsigned *)(MEMCTLBase + 0x70))
#define MEMC_CSALIAS0 ((volatile unsigned *)(MEMCTLBase + 0x74))
#define MEMC_CSALIAS1 ((volatile unsigned *)(MEMCTLBase + 0x78))
#define MEMC_CSREMAP0 ((volatile unsigned *)(MEMCTLBase + 0x84))
#define MEMC_CSREMAP1 ((volatile unsigned *)(MEMCTLBase + 0x88))
#define MEMC_SMTMGR_SET0 ((volatile unsigned *)(MEMCTLBase + 0x94))
#define MEMC_SMTMGR_SET1 ((volatile unsigned *)(MEMCTLBase + 0x98))
#define MEMC_SMTMGR_SET2 ((volatile unsigned *)(MEMCTLBase + 0x9c))
#define MEMC_FLASH_TRPDR ((volatile unsigned *)(MEMCTLBase + 0xA0))
#define MEMC_SMCTLR ((volatile unsigned *)(MEMCTLBase + 0xA4))
#define MEMC_FLASH_OPCODE ((volatile unsigned *)(MEMCTLBase + 0xA8))
#define MEMC_EXN_MODE_REG ((volatile unsigned *)(MEMCTLBase + 0xAC))
#define MEMC_SFCONR ((volatile unsigned *)(MEMCTLBase + 0xB0))
#define MEMC_SFCTLR ((volatile unsigned *)(MEMCTLBase + 0xB4))
#define MEMC_SFTMGR ((volatile unsigned *)(MEMCTLBase + 0xB8))
#define MEMC_SRAM ((volatile unsigned *)SRAMBase)
#define MEMC_FLASH ((volatile unsigned *)FLASHBase)
#define MEMC_SDRAM ((volatile unsigned *)SDRAMBase)
/*****************************************************************************/
/* Definition for MEMCTL Controller */
/*****************************************************************************/
/* MEMC_SCONR */
#define S_SDA_OE_N 20
#define S_SD 19
#define S_SCL 18
#define S_SA 15
#define S_DATA_WIDTH 13
#define S_COL_ADDR_WIDTH 9
#define S_ROW_ADDR_WIDTH 5
#define S_BANK_ADDR_WIDTH 3
/* MEMC_STMGR0,1 */
#define S_T_RC 22
#define S_T_XSR 18
#define S_T_RCAR 14
#define S_T_WR 12
#define S_T_RP 9
#define S_T_RCD 7
#define S_T_RAS_MIN 2
#define CAS_LATENCY 0
#define S_T_WTR 20
#define NUM_INIT_REF 16
#define S_T_INIT 0
/* MEMC_SCTLR */
#define EXN_MODE_REG_UPDATE 18
#define S_RD_READY_MODE 17
#define NUM_OPEN_BANKS 12
#define SELF_REFRESH_STATUS 11
#define SYNC_FLASH_SOFT_SEQ 10
#define SET_MODE_REG 9
#define READ_PIPE 6
#define FULL_REFRESH_AFTER_SR 5
#define FULL_REFRESH_BEFORE_SR 4
#define PRECHARGE_ALGORITHM 3
#define POWER_DOWN_MODE 2
#define SELF_REFRESH 1
#define INITIALIZE 0
/* MEMC_SREFR */
#define GPI 24
#define GPO 16
#define T_REF 0
/* MEMC_SCSLR0,1,2,3,4,5,6,7 */
#define SCSL 16
/* MEMC_SMSKR0,1,2,3,4,5,6,7 */
#define REG_SELECT 8
#define MEM_TYPE 5
#define MEM_SIZE 0
/* MEMC_CSALIAS0,1 */
#define CHIP_SELECT_ALIAS_ADDRESS 16
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