📄 socplatform.h
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/***************************************************************************
SCDMA-SoC Driver: socPlatform.h
****************************************************************************
Revision : 0.1
Date: 2003/07/23
Author: lilin
****************************************************************************/
/*****************************************************************************/
/* Base addresses for standard memory-mapped peripherals for DTT6C01A0410 */
/*****************************************************************************/
#define DMABase 0x20019800
#define MEMCTLBase 0x2001A000
#define LCDCBase 0x2001B000
#define ICTLBase 0x2001B800
#define RAPBase 0x2001C000
#define CPRBase 0x2001C400
#define WDT1Base 0x2001C800
#define RTCBase 0x2001CC00
#define AUXIFBase 0x2001D000
#define KBSBase 0x2001D400
#define PWMBase 0x2001D800
#define GPIO1Base 0x2001DC00
#define UART2Base 0x2001E000
#define UART1Base 0x2001E400
#define TIMERBase 0x2001E800
#define SIMBase 0x2001EC00
#define DPRAMBase 0x20018000
#define SRAMBase 0x04000000
#define FLASHBase 0x02000000
#define SDRAMBase 0x08000000
#define DPRAM2Base 0x80018000
#define MEMBase 0x20000
/*****************************************************************************/
/* ICTL interrupt Controller IRQ register for DTT6C01A0410 */
/*****************************************************************************/
#define ICTL_IRQ_INTEN ((volatile unsigned *)(ICTLBase + 0x00))
#define ICTL_IRQ_INTMASK ((volatile unsigned *)(ICTLBase + 0x08))
#define ICTL_IRQ_INTFORCE ((volatile unsigned *)(ICTLBase + 0x10))
#define ICTL_IRQ_RAWSTATUS ((volatile unsigned *)(ICTLBase + 0x18))
#define ICTL_IRQ_STATUS ((volatile unsigned *)(ICTLBase + 0x20))
#define ICTL_IRQ_MASKSTATUS ((volatile unsigned *)(ICTLBase + 0x28))
#define ICTL_IRQ_FINALSTATUS ((volatile unsigned *)(ICTLBase + 0x30))
#define ICTL_IRQ_VECTOR ((volatile unsigned *)(ICTLBase + 0x38))
#define ICTL_IRQ_VECTOR0 ((volatile unsigned *)(ICTLBase + 0x40))
#define ICTL_IRQ_VECTOR1 ((volatile unsigned *)(ICTLBase + 0x48))
#define ICTL_IRQ_VECTOR2 ((volatile unsigned *)(ICTLBase + 0x50))
#define ICTL_IRQ_VECTOR3 ((volatile unsigned *)(ICTLBase + 0x58))
#define ICTL_IRQ_VECTOR4 ((volatile unsigned *)(ICTLBase + 0x60))
#define ICTL_IRQ_VECTOR5 ((volatile unsigned *)(ICTLBase + 0x68))
#define ICTL_IRQ_VECTOR6 ((volatile unsigned *)(ICTLBase + 0x70))
#define ICTL_IRQ_VECTOR7 ((volatile unsigned *)(ICTLBase + 0x78))
#define ICTL_IRQ_VECTOR8 ((volatile unsigned *)(ICTLBase + 0x80))
#define ICTL_IRQ_VECTOR9 ((volatile unsigned *)(ICTLBase + 0x88))
#define ICTL_IRQ_VECTOR10 ((volatile unsigned *)(ICTLBase + 0x90))
#define ICTL_IRQ_VECTOR11 ((volatile unsigned *)(ICTLBase + 0x98))
#define ICTL_IRQ_VECTOR12 ((volatile unsigned *)(ICTLBase + 0xa0))
#define ICTL_IRQ_VECTOR13 ((volatile unsigned *)(ICTLBase + 0xa8))
#define ICTL_IRQ_VECTOR14 ((volatile unsigned *)(ICTLBase + 0xb0))
#define ICTL_IRQ_VECTOR15 ((volatile unsigned *)(ICTLBase + 0xb8))
#define ICTL_IRQ_PLEVEL ((volatile unsigned *)(ICTLBase + 0xd8))
#define ICTL_VERSION_ID ((volatile unsigned *)(ICTLBase + 0xe0))
/*****************************************************************************/
/* ICTL interrupt Controller FIQ register for DTT6C01A0410 */
/*****************************************************************************/
#define ICTL_FIQ_INTEN ((volatile unsigned *)(ICTLBase + 0xc0))
#define ICTL_FIQ_INTMASK ((volatile unsigned *)(ICTLBase + 0xc4))
#define ICTL_FIQ_INTFORCE ((volatile unsigned *)(ICTLBase + 0xc8))
#define ICTL_FIQ_RAWSTATUS ((volatile unsigned *)(ICTLBase + 0xcc))
#define ICTL_FIQ_STATUS ((volatile unsigned *)(ICTLBase + 0xd0))
#define ICTL_FIQ_FINALSTATUS ((volatile unsigned *)(ICTLBase + 0xd4))
/*****************************************************************************/
/* IRQ and FIQ numbers */
/*****************************************************************************/
#define MAXIRQNUM 21
#define MAXFIQNUM 0
#define NR_IRQS (MAXIRQNUM + 1)
#define NR_FIQS (MAXFIQNUM + 1)
/*****************************************************************************/
/* Definitions of IRQ and FIQ ids for DTT6C01A0410 */
/*****************************************************************************/
#define ICTL_IRQ_EXTINT0 0
#define ICTL_IRQ_TIMERINT2 1
#define ICTL_IRQ_TIMERINT0 2
#define ICTL_IRQ_UARTINT1 3
#define ICTL_IRQ_PWMINT 4
#define ICTL_IRQ_SIMINT 5
#define ICTL_IRQ_KBSINT 6
#define ICTL_IRQ_LCDINT 7
#define ICTL_IRQ_UARTINT2 8
#define ICTL_IRQ_TIMERINT1 9
#define ICTL_IRQ_AUXIFINT 10
#define ICTL_IRQ_RTCINT 11
#define ICTL_IRQ_DMAINT 12
#define ICTL_IRQ_GPIOINT0 13
#define ICTL_IRQ_EXTINT1 14
#define ICTL_IRQ_TIMERINT3 15
#define ICTL_IRQ_WDTINT 16
#define ICTL_IRQ_CPRINT 17
#define ICTL_IRQ_SSIINT1 18
#define ICTL_IRQ_SSIINT2 19
#define ICTL_IRQ_SSIINT3 20
#define ICTL_IRQ_GPIOINT1 21
#define ICTL_IRQ_UARTINT0 22
#define ICTL_FIQ_DPRAMINT 0
/*****************************************************************************/
/* TIMER Controller register for DTT6C01A0410 */
/*****************************************************************************/
#define TIMER0_LOAD ((volatile unsigned *)TIMERBase)
#define TIMER0_VALUE ((volatile unsigned *)(TIMERBase + 0x04))
#define TIMER0_CNTL ((volatile unsigned *)(TIMERBase + 0x08))
#define TIMER0_EOI ((volatile unsigned *)(TIMERBase + 0x0c))
#define TIMER0_STATUS ((volatile unsigned *)(TIMERBase + 0x10))
#define TIMER1_LOAD ((volatile unsigned *)(TIMERBase + 0x14))
#define TIMER1_VALUE ((volatile unsigned *)(TIMERBase + 0x18))
#define TIMER1_CNTL ((volatile unsigned *)(TIMERBase + 0x1c))
#define TIMER1_EOI ((volatile unsigned *)(TIMERBase + 0x20))
#define TIMER1_STATUS ((volatile unsigned *)(TIMERBase + 0x24))
#define TIMER2_LOAD ((volatile unsigned *)(TIMERBase + 0x28))
#define TIMER2_VALUE ((volatile unsigned *)(TIMERBase + 0x2c))
#define TIMER2_CNTL ((volatile unsigned *)(TIMERBase + 0x30))
#define TIMER2_EOI ((volatile unsigned *)(TIMERBase + 0x34))
#define TIMER2_STATUS ((volatile unsigned *)(TIMERBase + 0x38))
#define TIMER3_LOAD ((volatile unsigned *)(TIMERBase + 0x3c))
#define TIMER3_VALUE ((volatile unsigned *)(TIMERBase + 0x40))
#define TIMER3_CNTL ((volatile unsigned *)(TIMERBase + 0x44))
#define TIMER3_EOI ((volatile unsigned *)(TIMERBase + 0x48))
#define TIMER3_STATUS ((volatile unsigned *)(TIMERBase + 0x4c))
#define TIMERS_STATUS ((volatile unsigned *)(TIMERBase + 0xa0))
#define TIMERS_EOI ((volatile unsigned *)(TIMERBase + 0xa4))
#define TIMERS_RSTATUS ((volatile unsigned *)(TIMERBase + 0xa8))
/*****************************************************************************/
/* Bit Definition in Timerx Control Register for DTT6C01A0410 */
/*****************************************************************************/
#define TIMER_CNTL_EN 0
#define TIMER_CNTL_MODE 1
#define TIMER_CNTL_MASK 2
#define TIMER_FREE 0
#define TIMER_INTERVAL 1
/*****************************************************************************/
/* Counter/timer ids for DTT6C01A0410 */
/*****************************************************************************/
#define TIMER0 0
#define TIMER1 1
#define TIMER2 2
#define TIMER3 3
#define MAX_TIMER 3
#define MAX_PERIOD 0xffffffff
/* Timer definitions.
* The irq numbers of the individual timers
*/
#define TIMER_VECTORS { ICTL_IRQ_TIMERINT0, ICTL_IRQ_TIMERINT1, ICTL_IRQ_TIMERINT2, ICTL_IRQ_TIMERINT3}
/*
*/
/*****************************************************************************/
/* RAMAP Controller register for DTT6C01A0410 */
/*****************************************************************************/
#define RAP_PAUSE ((volatile unsigned *)RAPBase)
#define RAP_ID ((volatile unsigned *)(RAPBase + 0x04))
#define RAP_REMAP ((volatile unsigned *)(RAPBase + 0x08))
#define RAP_RST_STATUS ((volatile unsigned *)(RAPBase + 0x0c))
#define RAP_RST_CLEAR ((volatile unsigned *)(RAPBase + 0x10))
/*****************************************************************************/
/* Clock & Power Controller register for DTT6C01A0410 */
/*****************************************************************************/
#define CPR_SYSCLK ((volatile unsigned *)CPRBase)
#define CPR_PLLCR ((volatile unsigned *)(CPRBase + 0x04))
#define CPR_PWCR ((volatile unsigned *)(CPRBase + 0x08))
#define CPR_TIMERCLK ((volatile unsigned *)(CPRBase + 0x0c))
#define CPR_ARMCLK ((volatile unsigned *)(CPRBase + 0x10))
#define CPR_DSPCLK ((volatile unsigned *)(CPRBase + 0x14))
#define CPR_SLEEPCR ((volatile unsigned *)(CPRBase + 0x18))
#define CPR_WTC ((volatile unsigned *)(CPRBase + 0x1c))
#define CPR_WTI ((volatile unsigned *)(CPRBase + 0x20))
#define CPR_MEM_CNTRL ((volatile unsigned *)(CPRBase + 0x24))
#define CPR_AHBBCR ((volatile unsigned *)(CPRBase + 0x28))
#define CPR_DSPCR ((volatile unsigned *)(CPRBase + 0x2c))
#define CPR_STAR ((volatile unsigned *)(CPRBase + 0x30))
#define CPR_INTC ((volatile unsigned *)(CPRBase + 0x34))
#define CPR_AUX1_TIMER ((volatile unsigned *)(CPRBase + 0x38))
#define CPR_AUX2_TIMER ((volatile unsigned *)(CPRBase + 0x3c))
#define CPR_AUX3_TIMER ((volatile unsigned *)(CPRBase + 0x40))
/*****************************************************************************/
/* Definition for Module Control in Clock & Power Controller */
/*****************************************************************************/
#define CPR_SYS_PD 1
#define CPR_PLL_STOP 0
#define CPR_LOW_BAT 2
#define CPR_CHARGE_ON 1
#define CPR_PON_OFF 0
#define CPR_OP_UART1 9
#define CPR_OP_UART2 8
#define CPR_OP_UART3 7
#define CPR_OP_LCD 6
#define CPR_OP_AUX 5
#define CPR_OP_SPIF 4
#define CPR_OP_RFIF 3
#define CPR_OP_KBS 2
#define CPR_OP_SIM 1
#define CPR_OP_PWM 0
#define CPR_AWAKE_CLR 1
#define CPR_AWAKE_EN 0
#define CPR_SM_PD 11
#define CPR_SF_CLR 10
#define CPR_SDRAM_CLR 9
#define CPR_SF_PD 8
#define CPR_SDRAM_PD 7
#define CPR_PIPE_SEL 6
#define CPR_WR_CNTRL 3
#define CPR_RD_CNTRL 0
#define CPR_SYNC_BP 6
#define CPR_AHB1_CNTRL 3
#define CPR_AHB2_CNTRL 0
#define CPR_STOP_SLV 1
#define CPR_DSP_RST 0
#define CPR_SYS_INT 5
#define CPR_WT_INT 4
#define CPR_LP_INT 3
#define CPR_CHON_INT 2
#define CPR_CHOFF_INT 1
#define CPR_PONOFF_INT 0
#define ARM_CLK 0x00
#define DSP_CLK 0x01
#define HCLK1_CLK 0x02
#define HCLK2_CLK 0x03
#define M1638_CLK 0x04
#define K32_CLK 0x05
#define PCLK1_CLK 0x06
#define EXT_CLK 0x07
#define CLKMODE_1 0x00
#define CLKMODE_2 0x01
#define CLKMODE_3 0x02
#define CLKMODE_4 0x03
#define CLKMODE_5 0x04
#define CLKMODE_6 0x05
#define CLKMODE_7 0x06
#define CLKMODE_8 0x07
#define CLKMODE_9 0x08
#define CLKMODE_10 0x09
#define CLKMODE_11 0x0a
#define CLKMODE_12 0x0b
#define CLKMODE_13 0x0c
#define CLKMODE_14 0x0d
#define CLKMODE_15 0x0e
#define DIV_RATIO_1 0x00
#define DIV_RATIO_2 0x01
#define DIV_RATIO_4 0x02
#define DIV_RATIO_8 0x03
#define DIV_RATIO_16 0x04
#define DELAY_BYPASS 0x00
#define DELAY_UNIT_1 0x01
#define DELAY_UNIT_2 0x02
#define DELAY_UNIT_3 0x03
#define DELAY_UNIT_4 0x04
#define SYNC_NO_BYPASS 0x00
#define SYNC_BYPASS 0x01
#define MTTICK_CYCLE_0 0x00
#define MTTICK_CYCLE_10 0x01
#define MTTICK_CYCLE_20 0x02
#define MTTICK_CYCLE_40 0x03
#define MTTICK_CYCLE_80 0x04
#define MTTICK_CYCLE_160 0x05
#define MTTICK_CYCLE_320 0x06
#define CPR_ARM_CLK_OUT 0x00
#define CPR_DSP_CLK_OUT 0x01
#define CPR_HCLK_OUT 0x02
#define CPR_32K_CLK_OUT 0x03
#define CPR_PCLK1_OUT 0x04
#define CPR_PCLK2_OUT 0x05
#define CPR_RFIO_CLK_OUT 0x06
#define CPR_SPIF_CLK_OUT 0x07
/*****************************************************************************/
/* DMA Controller register for DTT6C01A0410 */
/*****************************************************************************/
#define DMA_SAR0 ((volatile unsigned *)DMABase)
#define DMA_DAR0 ((volatile unsigned *)(DMABase + 0x008))
#define DMA_LLR0 ((volatile unsigned *)(DMABase + 0x010))
#define DMA_CTL0_L ((volatile unsigned *)(DMABase + 0x018))
#define DMA_CTL0_H ((volatile unsigned *)(DMABase + 0x01c))
#define DMA_CFG0_L ((volatile unsigned *)(DMABase + 0x040))
#define DMA_CFG0_H ((volatile unsigned *)(DMABase + 0x044))
#define DMA_SAR1 ((volatile unsigned *)(DMABase + 0x058))
#define DMA_DAR1 ((volatile unsigned *)(DMABase + 0x060))
#define DMA_LLR1 ((volatile unsigned *)(DMABase + 0x068))
#define DMA_CTL1_L ((volatile unsigned *)(DMABase + 0x070))
#define DMA_CTL1_H ((volatile unsigned *)(DMABase + 0x074))
#define DMA_CFG1_L ((volatile unsigned *)(DMABase + 0x098))
#define DMA_CFG1_H ((volatile unsigned *)(DMABase + 0x09c))
#define DMA_SAR2 ((volatile unsigned *)(DMABase + 0x0b0))
#define DMA_DAR2 ((volatile unsigned *)(DMABase + 0x0b8))
#define DMA_LLR2 ((volatile unsigned *)(DMABase + 0x0c0))
#define DMA_CTL2_L ((volatile unsigned *)(DMABase + 0x0c8))
#define DMA_CTL2_H ((volatile unsigned *)(DMABase + 0x0cc))
#define DMA_CFG2_L ((volatile unsigned *)(DMABase + 0x0f0))
#define DMA_CFG2_H ((volatile unsigned *)(DMABase + 0x0f4))
#define DMA_SAR3 ((volatile unsigned *)(DMABase + 0x108))
#define DMA_DAR3 ((volatile unsigned *)(DMABase + 0x110))
#define DMA_LLR3 ((volatile unsigned *)(DMABase + 0x118))
#define DMA_CTL3_L ((volatile unsigned *)(DMABase + 0x120))
#define DMA_CTL3_H ((volatile unsigned *)(DMABase + 0x124))
#define DMA_CFG3_L ((volatile unsigned *)(DMABase + 0x148))
#define DMA_CFG3_H ((volatile unsigned *)(DMABase + 0x14C))
#define DMA_SAR4 ((volatile unsigned *)(DMABase + 0x160))
#define DMA_DAR4 ((volatile unsigned *)(DMABase + 0x168))
#define DMA_LLR4 ((volatile unsigned *)(DMABase + 0x170))
#define DMA_CTL4_L ((volatile unsigned *)(DMABase + 0x178))
#define DMA_CTL4_H ((volatile unsigned *)(DMABase + 0x182))
#define DMA_CFG4_L ((volatile unsigned *)(DMABase + 0x1a0))
#define DMA_CFG4_H ((volatile unsigned *)(DMABase + 0x1a4))
#define DMA_RAW_TRF ((volatile unsigned *)(DMABase + 0x2c0))
#define DMA_RAW_BLOCK ((volatile unsigned *)(DMABase + 0x2c8))
#define DMA_RAW_SRCTRAN ((volatile unsigned *)(DMABase + 0x2d0))
#define DMA_RAW_DSTTRAN ((volatile unsigned *)(DMABase + 0x2d8))
#define DMA_RAW_ERR ((volatile unsigned *)(DMABase + 0x2e0))
#define DMA_STATUS_TRF ((volatile unsigned *)(DMABase + 0x2e8))
#define DMA_STATUS_BLOCK ((volatile unsigned *)(DMABase + 0x2f0))
#define DMA_STATUS_SRCTRAN ((volatile unsigned *)(DMABase + 0x2f8))
#define DMA_STATUS_DSTTRAN ((volatile unsigned *)(DMABase + 0x300))
#define DMA_STATUS_ERR ((volatile unsigned *)(DMABase + 0x308))
#define DMA_MASK_TRF ((volatile unsigned *)(DMABase + 0x310))
#define DMA_MASK_BLOCK ((volatile unsigned *)(DMABase + 0x318))
#define DMA_MASK_SRCTRAN ((volatile unsigned *)(DMABase + 0x320))
#define DMA_MASK_DSTTRAN ((volatile unsigned *)(DMABase + 0x328))
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