isr.c

ISP1181MCU_FW_Ver1.01.zip是基于飞利浦ISP1181的USB HOST开发板固件源代码

/*
   //*************************************************************************
   //
   //                  P H I L I P S   P R O P R I E T A R Y
   //
   //           COPYRIGHT (c)   1999 BY PHILIPS SINGAPORE.
   //                     --  ALL RIGHTS RESERVED  --
   //
   // File Name:	ISR.C
   // Created:		Oct 24, 2000
   // Modified:
   // Revision:		1.01
   //
   //*************************************************************************
   //
   //*************************************************************************
   // Implementation Notes,
   //   ISR hierachy
   //       usb_isr()
   //
*/
#include <stdio.h>
#include <string.h>
#include <reg51.h>

#include "BasicTyp.h"
#include "common.h"

#include "USB100.h"

#include "HAL4Sys.h"
#include "HAL4D13.h"

#include "isr.h"
#include "mainloop.h"
//bulk by dma
#include "d13bus.h"

/*
//*************************************************************************
//  Public static data
//*************************************************************************
*/

D13FLAGS     bD13flags;

/* Control endpoint TX/RX buffers */
extern CONTROL_XFER ControlData;

/* ISR static vars */
IO_REQUEST idata ioRequest;
UCHAR idata GenEpBuf[NONISO_FIFOSIZE_8];
//dec19
UCHAR ioSize, ioCount;
//UCHAR xdata ExtRAMBuf[256];
UCHAR idata IntRAMBuf[64];

extern USHORT Hal4Sys_ClockTicks;

/*
//*************************************************************************
//  Private static data
//*************************************************************************
*/


/*
//*************************************************************************
//  ISR Subroutine
//*************************************************************************
*/
//dec19
extern BOOL bNoExtRAM;
/*
timer_isr() interrupt 1
{
	RaiseIRQL();

#ifdef WORK_AT_12MHZ
    TIMER0_LOW = 0x00;    // 1 MS interval @12MHz
	TIMER0_HIGH =TIMER0_AT12MHZ;    
#endif

#ifdef WORK_AT_24MHZ
    TIMER0_LOW = 0x00;    // 1 MS interval @24MHz
    TIMER0_HIGH =TIMER0_AT24MHZ;    
#endif

#ifdef WORK_AT_36MHZ
    TIMER0_LOW = 0x00;    // 1 MS interval @36MHz
    TIMER0_HIGH =TIMER0_AT36MHZ;    
#endif

#ifdef WORK_AT_48MHZ
    TIMER0_LOW = 0x00;    // 1 MS interval @36MHz
    TIMER0_HIGH =TIMER0_AT48MHZ;    
#endif

    Hal4Sys_ClockTicks++;
	bD13flags.bits.timer = 1;
    LowerIRQL();
//dec13, using timer INT to release bus to PIO
//	if(!(DMAINTRANSFER))
//	{
//		DMASTART = 0;
//	}
}
*/

usb_isr() interrupt 0
{
	ULONG   i_st;
	RaiseIRQL();

	if (ControlData.Abort)
	{
		Hal4Sys_WaitInUS(400);
		Hal4D13_LockDevice(0xAA37);
		Hal4Sys_WaitInUS(400);
		ControlData.Abort = 0;


	}

	i_st = Hal4D13_ReadInterruptRegister();

	if(i_st != 0)
	{
		if(i_st & D13REG_INTSRC_BUSRESET)
		{
			Isr_BusReset();
			bD13flags.bits.bus_reset = 1;
//from suspend state to wakeup?
//			bD13flags.bits.suspend = 0;
//			Hal4Sys_WaitInMS(15);
//			Hal4D13_LockDevice(0xAA37);//unlock device
		}
			if(i_st & D13REG_INTSRC_SUSPEND)
			{

			if(i_st & D13REG_INTSRC_BUSTATUS)
				{
				//current bus status is suspend
					Isr_SuspendChange();
					bD13flags.bits.suspend = 1;
				}
			}
		
			if(i_st & D13REG_INTSRC_RESUME)
			{
				Isr_Resume();
				bD13flags.bits.remote_wakeup = 1;
			}


			if(i_st & D13REG_INTSRC_EOT)
				Isr_DmaEot();
			if(i_st & D13REG_INTSRC_EP0IN)
				Isr_Ep00TxDone();
			if(i_st & D13REG_INTSRC_EP0OUT)     /*Keep Control Out of EP0 at Highest priority*/
				Isr_Ep00RxDone();
			if(i_st & D13REG_INTSRC_EP04)
				Isr_Ep04Done();
			if(i_st & D13REG_INTSRC_EP03)
				Isr_Ep03Done();
			if(i_st & D13REG_INTSRC_EP05)
				Isr_Ep05Done();
			if(i_st & D13REG_INTSRC_EP06)
				Isr_Ep06Done();
	}

}

void Isr_BusReset(void)
{
	config_endpoint();	
	bD13flags.bits.dma_state = DMA_IDLE;
}
void Isr_SuspendChange(void)
{
	Hal4D13_SetIntEnable(D13REG_INTSRC_EP0OUT\
				|D13REG_INTSRC_EP0IN\
				|D13REG_INTSRC_EP03|D13REG_INTSRC_EP04\
				|D13REG_INTSRC_BUSRESET\
				|D13REG_INTSRC_SUSPEND\
				|D13REG_INTSRC_RESUME);
				
	Hal4D13_SetMode(D13REG_MODE_SUSPND|D13REG_MODE_INT_EN|D13REG_MODE_SOFTCONNECT);
	Hal4D13_SetMode(D13REG_MODE_INT_EN|D13REG_MODE_SOFTCONNECT);

	ControlData.Abort = 1;
}

void Isr_Resume(void)
{
	//ww, july13
	Hal4D13_SetIntEnable(D13REG_INTSRC_EP0OUT|D13REG_INTSRC_EP0IN\
				|D13REG_INTSRC_EP03|D13REG_INTSRC_EP04\
				|D13REG_INTSRC_EP05|D13REG_INTSRC_EP06\
				|D13REG_INTSRC_SUSPEND\
				|D13REG_INTSRC_BUSRESET);


}


void Isr_DmaEot(void)
{

	if(bD13flags.bits.dma_state == DMA_PENDING)
		bD13flags.bits.setup_dma = 1;
	else
		bD13flags.bits.dma_state = DMA_IDLE;
}

/*
void Isr_SOF(void)
{
//	ISOLOOP(EPINDEX4EP05, EPINDEX4EP06, 64);
}
*/
void Isr_Ep00RxDone(void)
{
	UCHAR       ep_last, i;
//	USHORT      i_st;

	ep_last = Hal4D13_GetEndpointStatusWInteruptClear(EPINDEX4EP0_CONTROL_OUT); /* Clear interrupt flag */
//Jan10
/*	if (!(ep_last & D13REG_EPSTS_DBF0))
	{
//		cprintf("Fatal Error: Isr_Ep00RxDone GetEndpointStatus=%x\n",ep_last);
		// I can do nothing just return,
		return ;
	}
*/
	if (ep_last & D13REG_EPSTS_SETUP)
	{
//Aug 7, no need clear stall
//		Hal4D13_SetEndpointStatus(1, 0); //clear control in stall,
									// bug fix, not 100% effective
		
		// Getting Setup Packet
//Jan9, make enum clean
/*		
		switch( bD13flags.bits.DCP_state )
		{
		case USBFSM4DCP_SETUPPROC:
			
			// Abnormal case
			// Setup Transaction starts over the previous Setup Transaction.
			//
			
			// !!!Make sure fall thru!!!
			
		case USBFSM4DCP_DATAOUT:
			
			// Abnormal case
			// Setup Transaction starts within a broken transfer
			//
			// Host starts Setup Transaction in Data Out Stage of broken Control Transfer
			
			// !!!Make sure fall thru!!!
			
		case USBFSM4DCP_DATAIN:
			
			// Abnormal case
			// Setup Transaction starts within a broken transfer
			//
			// Host starts Setup Transaction in Data In Stage of broken Control Transfer
			
			// !!!Make sure fall thru!!!
			
		case USBFSM4DCP_REQUESTPROC:
			ControlData.Abort = 1;
			
			// !!!Make sure fall thru!!!
			
		case USBFSM4DCP_HANDSHAKE:
		case USBFSM4DCP_STALL :
		case USBFSM4DCP_IDLE :
//Aug 3
//		case USBFSM4DCP_CONTROLOUTDONE:
			bD13flags.bits.DCP_state = USBFSM4DCP_SETUPPROC;	//Normal !!!
//			cprintf("bD13flags.bits.DCP_state = x%hx\n", bD13flags.bits.DCP_state);
			break;
		default:
*/			
			// abnormal case
			// No such case
		
			bD13flags.bits.DCP_state = USBFSM4DCP_SETUPPROC;
//Jan9			break;
//Jan9		}
	}
	else /* not a setup packet, just a Data Out Packet */
	{
		switch (bD13flags.bits.DCP_state)
		{
		case USBFSM4DCP_DATAOUT:
			/*
			// Normal Path
			// Data out Stage of In Control Write Transfer.
			//
			// In the worst case,
			// if a Setup Packet came
			//  Because no AckSetup , No successive Data Out is allowed
			//  Because no StallEp0 , No stall will return.
			//
			*/
			i =	Hal4D13_ReadEndpoint(EPINDEX4EP0_CONTROL_OUT, ControlData.dataBuffer + ControlData.wCount,
				EP0_PACKET_SIZE);

			ControlData.wCount += i;
			if( i != EP0_PACKET_SIZE || ControlData.wCount >= ControlData.wLength)
			{
				bD13flags.bits.DCP_state = USBFSM4DCP_REQUESTPROC;
//Sept 11, NOT WORK
//				Chap9_SingleTransmitEP0(0, 0);
//
			} /* else  in state of USBFSM4DCP_DATAOUT */
			break;
		case USBFSM4DCP_HANDSHAKE:
			/*
			// it may or may not be zero Length Packet in the STATUS stage of Get Command,
			*/
			/*
			// According to USB1.1 8.5.2.1
			// Any Length Pkt issued by host is taken as valid status stage
			*/
//ww test=========check h/s stage: should be 0-length pkt
//			i =	Hal4D13_ReadEndpoint(EPINDEX4EP0_CONTROL_OUT, ControlData.dataBuffer + ControlData.wCount,
//				EP0_PACKET_SIZE);
//				cprintf("Status Stage: Out data length = x%hx\n", i);
//================			
			bD13flags.bits.DCP_state = USBFSM4DCP_IDLE;
//			cprintf("bD13flags.bits.DCP_state = x%hx\n", bD13flags.bits.DCP_state);
			/* D13 has Ack it in hardware, otherwise I cannot receive this interrupt*/
			break;
//Jan10
/*		case USBFSM4DCP_STALL:
			// After STALL,Except SETUP Token, No other token is allowed
		
			// !!!Make sure FAll THRU!!! 
			// jiang qian, already stalled been stalled.

				break;
*/
//Jan10, make ISR clear		case USBFSM4DCP_SETUPPROC:
			/*
			//In SETUPPROC, no Data-out phase shall occur.
			*/
			/* !!!Make sure FAll THRU!!! */
//Jan10, make ISR clear		case USBFSM4DCP_REQUESTPROC:

			/* !!!Make sure FAll THRU!!! */
//Jan10, make ISR clear	   case USBFSM4DCP_DATAIN:
			/*
			// Only IN token not Out Token is expected
			*/
			/* !!!Make sure FAll THRU!!! */
		default:
			/*
			// Anyway Stall it
			*/
			bD13flags.bits.DCP_state = USBFSM4DCP_STALL;
			Hal4D13_StallEP0InControlWrite();
			break;
		}
	}
	return ;
}

void Isr_Ep00TxDone(void)
{
	short i = ControlData.wLength - ControlData.wCount;
	UCHAR ep_last;

	ep_last = Hal4D13_GetEndpointStatusWInteruptClear(EPINDEX4EP0_CONTROL_IN); /* Clear interrupt flag */


	switch (bD13flags.bits.DCP_state)
	{
	case USBFSM4DCP_HANDSHAKE:
		break;
	case USBFSM4DCP_DATAIN:
		if( i >= EP0_PACKET_SIZE)
		{
			Hal4D13_WriteEndpoint(EPINDEX4EP0_CONTROL_IN,ControlData.Addr.pData + ControlData.wCount, EP0_PACKET_SIZE);
			ControlData.wCount += EP0_PACKET_SIZE;

			/*
			// State remains at USBFSM4DCP_DATAIN
			*/
		}
		else if( i != 0)
		{
			Hal4D13_WriteEndpoint(1, ControlData.Addr.pData + ControlData.wCount, i);
			ControlData.wCount += i;

			/*
			// Go to Handshake state, let HOST send 0-length Pkt.
			*/
			bD13flags.bits.DCP_state = USBFSM4DCP_HANDSHAKE;
		}
		else if (i == 0)
		{
			/*
			// Go to Handshake state, let HOST send 0-length Pkt.
			*/

			Hal4D13_SingleTransmitEP0(0, 0);
			bD13flags.bits.DCP_state = USBFSM4DCP_HANDSHAKE;

		}
		break;
	default:

		bD13flags.bits.DCP_state = USBFSM4DCP_STALL;
		Hal4D13_StallEP0InControlRead();
		break;
	}
}



void Isr_Ep03Done(void)
{
//bulk out
	UCHAR       ep_last, DoubleBuff=1;
	UCHAR		len;

	ep_last = Hal4D13_GetEndpointStatusWInteruptClear(EPINDEX4EP03); // Clear interrupt flag 

	if((ep_last & 0x60) == 0x60)
			DoubleBuff = 2;
	else
			DoubleBuff = 1;

	while(DoubleBuff)
	{
		if (ioCount <= ioSize)
		{
			if((ioSize-ioCount) >64)
				len = 64;
			else
			{
				len = ioSize - ioCount;

				if(bD13flags.bits.dma_state == DMA_PENDING)
					bD13flags.bits.setup_dma = 1;
				else
					bD13flags.bits.dma_state = DMA_IDLE;
			}
			ioCount += Hal4D13_ReadEndpoint(EPINDEX4EP03, IntRAMBuf+ioCount, len);
		}
		else
		{
			Hal4D13_ClearBuffer(EPINDEX4EP03);
			if(bD13flags.bits.dma_state == DMA_PENDING)
				bD13flags.bits.setup_dma = 1;
			else
				bD13flags.bits.dma_state = DMA_IDLE;
		}
		DoubleBuff --;

		if(DoubleBuff == 1)
			ep_last = Hal4D13_GetEndpointStatusWInteruptClear(EPINDEX4EP03); // Clear interrupt flag 

			
	}
}

void Isr_Ep04Done(void)
{
//bulk in
	UCHAR len;
	UCHAR		ep_last, DoubleBuff=1;


	ep_last = Hal4D13_GetEndpointStatusWInteruptClear(EPINDEX4EP04); // Clear interrupt flag

	if((ep_last & (D13REG_EPSTS_DBF0|D13REG_EPSTS_DBF1)) == 0x00)
		DoubleBuff = 2;
	else
		DoubleBuff = 1;

	while(DoubleBuff)
	{
		len = ioSize - ioCount;

		if((len == 0))
		{
			if(bD13flags.bits.dma_state == DMA_PENDING)
				bD13flags.bits.setup_dma = 1;
			else
				bD13flags.bits.dma_state = DMA_IDLE;
		}
		else
		{
			if(len > 64)
				len = 64;
			else
			{
				if(bD13flags.bits.dma_state == DMA_PENDING)
					bD13flags.bits.setup_dma = 1;
				else
					bD13flags.bits.dma_state = DMA_IDLE;
			}
			ioCount += Hal4D13_WriteEndpoint(EPINDEX4EP04, IntRAMBuf +ioCount, len);
		}
		DoubleBuff--;
	}
}

void Isr_Ep05Done(void)
{
	ISOLOOP(EPINDEX4EP05, EPINDEX4EP06, 64);
}
void Isr_Ep06Done(void)
{
}

/*
//*********************************************************************
// supporting Functions
//*********************************************************************
*/