2407e.h

PID典型算法

extern volatile unsigned int *IMR; 		/* Interrupt Mask Register*/
extern volatile unsigned int *IFR; 		/* Interrupt Flag Register*/

/* System configuration and interrupt registers*/

extern volatile unsigned int *SCSR1;		/* System Control & Status register. 1 */
extern volatile unsigned int *SCSR2; 		/* System Control & Status register. 2*/
extern volatile unsigned int *DINR; 			/* Device Identification Number register. */
extern volatile unsigned int *PIVR; 		    /* Peripheral Interrupt Vector register. */
extern volatile unsigned int *PIRQR0; 		/* Peripheral Interrupt Request register 0*/
extern volatile unsigned int *PIRQR1; 		/* Peripheral Interrupt Request register 1*/
extern volatile unsigned int *PIRQR2; 		/* Peripheral Interrupt Request register 2*/
extern volatile unsigned int *PIACKR0; 		/* Peripheral Interrupt Acknowledge register 0 */
extern volatile unsigned int *PIACKR1; 		/* Peripheral Interrupt Acknowledge register 1 */
extern volatile unsigned int *PIACKR2; 		/* Peripheral Interrupt Acknowledge register 2*/

/* External interrupt configuration registers */

extern volatile unsigned int *XINT1CR; 		/* External interrupt 1 control register*/
extern volatile unsigned int *XINT2CR; 	    /* External interrupt 2 control register*/

/* Digital I/O registers*/

extern volatile unsigned int *MCRA;			/* I/O Mux Control Register A*/
extern volatile unsigned int *MCRB; 			/* I/O Mux Control Register B*/
extern volatile unsigned int *MCRC; 			/* I/O Mux Control Register C*/
extern volatile unsigned int *PADATDIR; 		/* I/O port A Data & Direction register*/
extern volatile unsigned int *PBDATDIR; 		/* I/O port B Data & Direction register*/
extern volatile unsigned int *PCDATDIR; 		/* I/O port C Data & Direction register*/
extern volatile unsigned int *PDDATDIR; 		/* I/O port D Data & Direction register*/
extern volatile unsigned int *PEDATDIR; 		/* I/O port E Data & Direction register*/
extern volatile unsigned int *PFDATDIR; 		/* I/O port F Data & Direction register*/

/* Watchdog (WD) registers*/

extern volatile unsigned int *WDCNTR; 		/* WD Counter register */
extern volatile unsigned int *WDKEY; 		/* WD Key register*/
extern volatile unsigned int *WDCR;			/* WD Control register*/

/* ADC registers*/

extern volatile unsigned int *ADCTRL1; 		/* ADC Control register 1*/
extern volatile unsigned int *ADCTRL2; 		/* ADC Control register 2*/
extern volatile unsigned int *MAXCONV;		/* Maximum conversion channels register*/
extern volatile unsigned int *CHSELSEQ1;		/* Channel select Sequencing control register 1*/
extern volatile unsigned int *CHSELSEQ2; 	/* Channel select Sequencing control register 2*/
extern volatile unsigned int *CHSELSEQ3; 	/* Channel select Sequencing control register 3*/
extern volatile unsigned int *CHSELSEQ4; 	/* Channel select Sequencing control register 4*/
extern volatile unsigned int *AUTO_SEQ_SR; 	/* Auto杝equence status register*/
extern volatile unsigned int *RESULT0; 		/* Conversion result buffer register 0*/
extern volatile unsigned int *RESULT1; 		/* Conversion result buffer register 1*/
extern volatile unsigned int *RESULT2; 		/* Conversion result buffer register 2*/
extern volatile unsigned int *RESULT3; 		/* Conversion result buffer register 3 */
extern volatile unsigned int *RESULT4; 		/* Conversion result buffer register 4*/
extern volatile unsigned int *RESULT5; 		/* Conversion result buffer register 5*/
extern volatile unsigned int *RESULT6;		/* Conversion result buffer register 6*/
extern volatile unsigned int *RESULT7; 		/* Conversion result buffer register 7*/
extern volatile unsigned int *RESULT8; 		/* Conversion result buffer register 8*/
extern volatile unsigned int *RESULT9;		/* Conversion result buffer register 9 */
extern volatile unsigned int *RESULT10; 		/* Conversion result buffer register 10*/
extern volatile unsigned int *RESULT11; 		/* Conversion result buffer register 11*/
extern volatile unsigned int *RESULT12; 		/* Conversion result buffer register 12*/
extern volatile unsigned int *RESULT13; 		/* Conversion result buffer register 13*/
extern volatile unsigned int *RESULT14; 		/* Conversion result buffer register 14*/
extern volatile unsigned int *RESULT15; 		/* Conversion result buffer register 15*/
extern volatile unsigned int *CALIBRATION; 	/* Calib result, used to correct*/
			 	/* subsequent conversions*/


/* SPI registers*/

extern volatile unsigned int *SPICCR; 		/* SPI Config Control register*/
extern volatile unsigned int *SPICTL; 		/* SPI Operation Control register*/
extern volatile unsigned int *SPISTS; 		/* SPI Status register*/
extern volatile unsigned int *SPIBRR; 		/* SPI Baud rate control register*/
extern volatile unsigned int *SPIRXEMU; 		/* SPI Emulation buffer register*/
extern volatile unsigned int *SPIRXBUF; 		/* SPI Serial receive buffer register*/
extern volatile unsigned int *SPITXBUF; 		/* SPI Serial transmit buffer register*/
extern volatile unsigned int *SPIDAT; 		/* SPI Serial data register*/
extern volatile unsigned int *SPIPRI; 		/* SPI Priority control register*/


/* SCI registers*/

extern volatile unsigned int *SCICCR; 		/* SCI Communication control register */
extern volatile unsigned int *SCICTL1;		/* SCI Control register 1*/
extern volatile unsigned int *SCIHBAUD; 		/* SCI Baud Rate MS byte register */
extern volatile unsigned int *SCILBAUD; 		/* SCI Baud Rate LS byte register*/
extern volatile unsigned int *SCICTL2 ;		/* SCI Control register 2*/
extern volatile unsigned int *SCIRXST ;		/* SCI Receiver Status register*/
extern volatile unsigned int *SCIRXEMU ;		/* SCI Emulation Data Buffer register */
extern volatile unsigned int *SCIRXBUF; 		/* SCI Receiver Data buffer register*/
extern volatile unsigned int *SCITXBUF; 		/* SCI Transmit Data buffer register*/
extern volatile unsigned int *SCIPRI; 			/* SCI Priority control register*/


/* Event Manager A (EVA) registers*/

extern volatile unsigned int *GPTCONA; 		/* GP Timer control register A*/
extern volatile unsigned int *T1CNT; 		/* GP Timer 1 counter register*/
extern volatile unsigned int *T1CMPR; 		/* GP Timer 1 compare register*/
extern volatile unsigned int *T1PR ;			/* GP Timer 1 period register*/
extern volatile unsigned int *T1CON ;		/* GP Timer 1 control register*/
extern volatile unsigned int *T2CNT ;		/* GP Timer 2 counter register*/
extern volatile unsigned int *T2CMPR; 		/* GP Timer 2 compare register*/
extern volatile unsigned int *T2PR ;			/* GP Timer 2 period register*/
extern volatile unsigned int *T2CON; 		/* GP Timer 2 control register*/

extern volatile unsigned int *COMCONA; 		/* Compare control register A */
extern volatile unsigned int *ACTRA ;		/* Full compare Action control register A*/
extern volatile unsigned int *DBTCONA ;	    /* Dead朾and timer control register A */

extern volatile unsigned int *CMPR1 ;		/* Full compare unit compare register1 */
extern volatile unsigned int *CMPR2 ;		/* Full compare unit compare register2 */
extern volatile unsigned int *CMPR3;		/* Full compare unit compare register3 */

extern volatile unsigned int *CAPCONA; 	    /* Capture control register A*/
extern volatile unsigned int *CAPFIFOA; 		/* Capture FIFO status register A */

extern volatile unsigned int *CAP1FIFO ;		/* Capture Channel 1 FIFO Top*/
extern volatile unsigned int *CAP2FIFO; 		/* Capture Channel 2 FIFO Top*/
extern volatile unsigned int *CAP3FIFO; 		/* Capture Channel 3 FIFO Top*/

extern volatile unsigned int *CAP1FBOT; 		/* Bottom reg. of capture FIFO stack 1*/