w90p710_init.s__

基于华邦W90P710arm7嵌入式处理器的bootloader程序

;******************************************************************************
;* 文件名		: init.s
;* 版本			: 
;* 日期			: 
;* 概述			: 复位异常向量的服务程序是系统的初始化。在本例中未设定其他异常
; 				  向量，读者可在自行编写，以满足特定系统的需求。
;******************************************************************************


;******************************************************	
;System memory define
;******************************************************  
Mode_USR        EQU		0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UNDEF      EQU     0x1B
Mode_SYS        EQU     0x1F

I_Bit           EQU     0x80 ; when I bit is set, IRQ is disabled
F_Bit           EQU     0x40 ; when F bit is set, FIQ is disabled

EBICON			EQU		0xFFF01000	;EBI control register
ROMCON			EQU		0xFFF01004	;ROM/FLASH control register
SDCONF0			EQU		0xFFF01008	;SDRAM bank 0 configuration register
SDCONF1			EQU		0xFFF0100C	;SDRAM bank 1 configuration register
SDTIME0			EQU		0xFFF01010	;SDRAM bank 0 timing control register
SDTIME1			EQU		0xFFF01014	;SDRAM bank 1 timing control register

RAM_Limit       EQU     0x8000

UND_Stack		EQU		RAM_Limit
Abort_Stack		EQU		RAM_Limit-256
IRQ_Stack       EQU     RAM_Limit-512       ; followed by IRQ stack
FIQ_Stack       EQU     RAM_Limit-768       ; followed by IRQ stack
SVC_Stack       EQU     RAM_Limit-1024      ; SVC stack at top of memory
USR_Stack       EQU     0x7000	       ; followed by USR(SYS) stack
	
	EXPORT	Reset_Handler
    AREA Init, CODE, READONLY
        ENTRY

Reset_Handler
;******************************************************	
;Disable all interrupt
;******************************************************
		MRS		r0, CPSR
		ORR		r0, r0, #0xC0
		MSR		CPSR_c, r0

;******************************************************	
;Initialise the system memory
;****************************************************** 
   		ADRL    r0, Init_SystemMemory
 		LDMIA   r0, {r1-r6}
 		LDR		r0, =EBICON
 		STMIA   r0, {r1-r6}
 		
;******************************************************	
;Copy rom to sdram
;****************************************************** 		
		LDR		r0, =0x0		;the start address of rom
		LDR		r1, =0x400000	;the size of rom
		LDR		r2, =0x400000	;the start address of sdram
Copy_Loop
		LDR		r3, [r0], #4
		STR		r3, [r2], #4
		SUBS	r1, r1, #4
		BNE		Copy_Loop
		
;******************************************************	
;Remap the system memory
;******************************************************
   		ADRL    r0, Remap_SystemMemory
 		LDMIA   r0, {r1-r6}
 		LDR		r0, =EBICON
 		STMIA   r0, {r1-r6} 

;******************************************************	
;Initialise stack pointer registers
;******************************************************
        MSR     CPSR_c, #Mode_UNDEF:OR:I_Bit:OR:F_Bit
        LDR     SP, =UND_Stack

        MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit 
        LDR     SP, =Abort_Stack

        MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
        LDR     SP, =IRQ_Stack

        MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
        LDR     SP, =FIQ_Stack

        MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
        LDR     SP, =SVC_Stack
       
        MSR     CPSR_c, #Mode_SYS:OR:I_Bit:OR:F_Bit
        LDR     SP, =USR_Stack
        
;******************************************************	
;Enable all interrupt
;******************************************************        
		MRS		r0, CPSR 
		BIC		r0, r0, #0xC0
		MSR 	CPSR_c, r0
		MSR		CPSR_c, #Mode_USR
		
;******************************************************	
;Entry main()
;******************************************************		
		IMPORT	__main
		B		__main 
		B		.

		
Init_SystemMemory
		DCD		0x000530C1					
		DCD		0x00040084					; ROMCON(Flash) 
		DCD		0x008010E4					; 16M(4Mx16x2)		
		DCD		0x00000000					 
		DCD		0x0000014B					
		DCD		0x00000000					

Remap_SystemMemory
		DCD		0x000530C1					
		DCD		0x02040084					; ROMCON(Flash) 
		DCD		0x000010E4					; 16M(4Mx16x2) 		
		DCD		0x00000000					   
		DCD		0x0000014B					 
		DCD		0x00000000					 

        END