📄 fei82557end.h
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/* fei82557End.h - Intel 82557 network interface header *//* Copyright 1990-1998 Wind River Systems, Inc. *//*modification history--------------------01e,21jul98,cn Moved here some redefineable macros01d,01apr98,cn added vendor and device id definitions01c,11mar98,cn checked-in01b,05mar98,cn code clean-up after code review01a,07nov97,cn created from ../netif/if_fei.h, version 01c*/#ifndef __INCfei82557Endh#define __INCfei82557Endh/* includes */#include "etherLib.h"#ifdef __cplusplusextern "C" {#endif#if ((CPU_FAMILY==I960) && (defined __GNUC__))#pragma align 1 /* tell gcc960 not to optimize alignments */#endif /* CPU_FAMILY==I960 *//* defines *//* * redefine the macro below in the bsp if you need to access the device * registers/descriptors in a more suitable way. */#ifndef FEI_LONG_WR#define FEI_LONG_WR(addr, value) \ (* (UINT32 *) (addr) = ((UINT32) (FEI_SWAP_LONG (value) & 0xffffffff)))#endif /* FEI_LONG_WR */ #ifndef FEI_WORD_WR#define FEI_WORD_WR(addr, value) \ (* (UINT16 *) (addr) = ((UINT16) (FEI_SWAP_WORD (value) & 0x0000ffff)))#endif /* FEI_WORD_WR */ #ifndef FEI_BYTE_WR#define FEI_BYTE_WR(addr, value) \ (* ((UINT8 *) (addr)) = ((UINT8) ((value) & 0x000000ff)))#endif /* FEI_BYTE_WR */ #ifndef FEI_LONG_RD#define FEI_LONG_RD(addr, value) \ (((UINT32) (value)) = (UINT32) FEI_SWAP_LONG (((* (addr)) & 0xffffffff)))#endif /* FEI_LONG_RD */ #ifndef FEI_WORD_RD#define FEI_WORD_RD(addr, value) \ (((UINT16) (value)) = (UINT16) FEI_SWAP_WORD (((* (addr)) & 0xffff)))#endif /* FEI_WORD_RD */ #ifndef FEI_BYTE_RD#define FEI_BYTE_RD(addr, value) \ (((UINT8) (value)) = (UINT8) (((* (addr)) & 0x000000ff)))#endif /* FEI_BYTE_RD */ /* * Default macro definitions for BSP interface. * These macros can be redefined in a wrapper file, to generate * a new module with an optimized interface. */ #ifndef SYS_INT_CONNECT#define SYS_INT_CONNECT(pDrvCtrl, pFunc, arg, pRet) \{ \*pRet = OK; \ \if (FEI_VECTOR (pDrvCtrl)) \ { \ *pRet = (feiEndIntConnect) ((VOIDFUNCPTR*) \ INUM_TO_IVEC (FEI_VECTOR (pDrvCtrl)), \ (pFunc), (int) (arg)); \ } \}#endif /* SYS_INT_CONNECT */ #ifndef SYS_INT_DISCONNECT#define SYS_INT_DISCONNECT(pDrvCtrl, pFunc, arg, pRet) \{ \*pRet = OK; \ \if (FEI_VECTOR (pDrvCtrl) && (feiEndIntDisconnect != NULL)) \ { \ *pRet = feiEndIntDisconnect ((VOIDFUNCPTR*) \ INUM_TO_IVEC (FEI_VECTOR (pDrvCtrl)), \ (pFunc)); \ } \}#endif /* SYS_INT_DISCONNECT */ #ifndef SYS_INT_ENABLE#define SYS_INT_ENABLE(pDrvCtrl) \if (FEI_INT_ENABLE (pDrvCtrl)) \ ((*(FUNCPTR) (FEI_INT_ENABLE (pDrvCtrl))) (pDrvCtrl->board.vector))#endif /*SYS_INT_ENABLE*/ #ifndef SYS_INT_DISABLE#define SYS_INT_DISABLE(pDrvCtrl) \if (FEI_INT_DISABLE (pDrvCtrl)) \ ((*(FUNCPTR) (FEI_INT_DISABLE (pDrvCtrl))) (pDrvCtrl->board.vector))#endif /*SYS_INT_DISABLE*/ #ifndef SYS_INT_ACK#define SYS_INT_ACK(pDrvCtrl) \if (FEI_INT_ACK (pDrvCtrl)) \ ((*(FUNCPTR) (FEI_INT_ACK (pDrvCtrl))) (pDrvCtrl->unit))#endif /*SYS_INT_ACK*/ #ifndef LOCAL_TO_SYS_ADDR#define LOCAL_TO_SYS_ADDR(unit,localAddr) \ ((int) pDrvCtrl->board.sysLocalToBus ? \ (*pDrvCtrl->board.sysLocalToBus) (unit, localAddr) : localAddr)#endif /* LOCAL_TO_SYS_ADDR */ #ifndef SYS_TO_LOCAL_ADDR#define SYS_TO_LOCAL_ADDR(unit,sysAddr) \ ((int) pDrvCtrl->board.sysBusToLocal ? \ (*pDrvCtrl->board.sysBusToLocal)(unit, sysAddr) : sysAddr)#endif /* SYS_TO_LOCAL_ADDR */ /* Intel PRO-100B PCI specific definitions */ #define PRO100B_PCI_VENDOR_ID 0x8086 /* PCI vendor ID */#define PRO100B_PCI_DEVICE_ID 0x1229 /* PCI device ID */ #define MC_FEI MC_EI /* temp */#define DEV_NAME "fei"#define DEV_NAME_LEN 4#define DEF_NUM_CFDS 32 /* default number of CFDs */#define DEF_NUM_RFDS 32 /* default number of RFDs */#define FEI_100MBS 100000000 /* bits per sec */#define FEI_10MBS 10000000 /* bits per sec */#define EADDR_LEN 6 /* ethernet address length */#define FEI_ADDR_LEN EADDR_LEN /* ethernet address length */ #define FEI_ACTION_TMO 0x01 /* action command timeout in seconds */#define FEI_SCB_TMO 0x01 /* SCB command timeout in seconds */#define FEI_INIT_TMO 0x01 /* 557 init timeout in seconds */#define FEI_TX_RESTART_TMO 0x01 /* tx restart watchdog timeout */#define FEI_TCB_TX_THRESH 0x10 /* Tx threshold value */ /* RFD and CFD size */ #define RFD_SIZE_HDR 16#define RFD_SIZE_PKT (EH_SIZE + ETHERMTU + 2)#define RFD_SIZE_TRAIL RFD_SIZE_PREV#define RFD_SIZE_PREV 4 #define RFD_SIZE ROUND_UP ((RFD_SIZE_HDR + \ RFD_SIZE_PKT + \ RFD_SIZE_TRAIL), 4) #define CFD_SIZE_HDR 8#define CFD_SIZE_DUMP 4#define CFD_SIZE_MULTIC (2 + (6 * N_MCAST))#define CFD_SIZE_IA 8#define CFD_SIZE_NOP 0#define CFD_SIZE_PKT (EH_SIZE + ETHERMTU + 2)#define CFD_SIZE_TCB (8 + CFD_SIZE_PKT)#define CFD_SIZE_PREV 4#define CFD_SIZE_ACTION 1#define CFD_SIZE_TRAIL (CFD_SIZE_PREV + CFD_SIZE_ACTION)#define CFD_SIZE_CORE CFD_SIZE_TCB #define CFD_SIZE ROUND_UP ((CFD_SIZE_HDR + \ CFD_SIZE_CORE + \ CFD_SIZE_TRAIL), 4) /* frame descriptors definitions */ #define CFD_STAT_OFFSET 0x00 /* status word */#define CFD_COMM_OFFSET 0x02 /* command word */#define CFD_NEXT_OFFSET 0x04 /* next frame */#define CFD_PREV_OFFSET (CFD_SIZE - 4) /* previous frame */#define CFD_TBD_OFFSET 0x08 /* buffer descriptor*/#define CFD_COUNT_OFFSET 0x0c /* count field */#define CFD_NUM_OFFSET 0x0f /* buffer num field */#define CFD_THRESH_OFFSET 0x0e /* threshold field */#define CFD_ACTION_OFFSET (CFD_SIZE - 5) /* action/transmit */#define CFD_PKT_OFFSET (CFD_SIZE_HDR + 8) /* packet data */#define CFD_IA_OFFSET CFD_SIZE_HDR /* individual address */#define CFD_MCOUNT_OFFSET CFD_SIZE_HDR /* mcount field */#define CFD_MC_OFFSET (CFD_SIZE_HDR + 2) /* mcast list */ #define RFD_STAT_OFFSET 0x00 /* status word */#define RFD_COMM_OFFSET 0x02 /* command word */#define RFD_NEXT_OFFSET 0x04 /* next frame field */#define RFD_PREV_OFFSET (RFD_SIZE - 4) /* previous frame */#define RFD_RBD_OFFSET 0x08 /* buffer descriptor */#define RFD_COUNT_OFFSET 0x0c /* count field */#define RFD_SIZE_OFFSET 0x0e /* data size */#define RFD_PKT_OFFSET (RFD_SIZE_HDR) /* packet data*/ #define TBD_NOT_USED 0xffffffff /* use semplified mode */#define RBD_NOT_USED 0xffffffff /* use semplified mode *//* board specific infomation */typedef struct { UINT32 vector; /* interrupt vector number */ UINT32 baseAddr; /* memory base address for CSR */ UCHAR enetAddr[6]; /* ethernet address */ int (*intEnable)(int unit); /* board specific interrupt enable routine */ int (*intDisable)(int unit); /* board specific interrupt disable routine */ int (*intAck) (int unit); /* interrupt ack */ UINT32 (*sysLocalToBus)(int unit,UINT32 localAdr); UINT32 (*sysBusToLocal)(int unit,UINT32 sysAdr); /* configuration parameters, user can override in the BSP */ UINT8 phyAddr; /* PHY device address, valid addresses: 0-32 */ UINT8 phySpeed; UINT8 phyDpx;
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