u-boot-1.2.0-edb93xx_support.diff

u-boot 1.2.0 for ep93

+       free(dev.rx_sq.base);
+       /* Fall through */
+
+eth_init_failed_3:
+       free(dev.rx_dq.base);
+       /* Fall through */
+
+eth_init_failed_2:
+       free(dev.tx_sq.base);
+       /* Fall through */
+
+eth_init_failed_1:
+       free(dev.tx_dq.base);
+       /* Fall through */
+
+eth_init_failed_0:
+eth_init_done:
+       TRACE(("-eth_init %d", ret));
+       return(ret);
+}
+
+
+/**
+ * Copy a frame of data from the MAC into the protocol layer for further
+ * processing.
+ *
+ * TODO: Enhance this to deal with as many packets as are available at
+ * the MAC at one time? */
+extern int eth_rx(void)
+{
+       int ret = ETH_STATUS_FAILURE;
+       int nbytes_frame = 0;
+       int nbytes_fragment = 0;
+       void *dest = (void *)NetRxPackets[0];
+
+       TRACE(("+eth_rx"));
+
+       while (1) {
+               if (dev.rx_sq.current->rfp && dev.rx_sq.current->rwe) {
+                       /* We have a good frame.  Extract the frame's length
+                        * from the current rx_status_queue entry, and copy
+                        * the frame's data into NetRxPackets[] of the
+                        * protocol stack.  We track the total number of
+                        * bytes in the frame (nbytes_frame) which will be
+                        * used when we pass the data off to the protocol
+                        * layer via NetReceive(). */
+                       nbytes_fragment = dev.rx_sq.current->frame_length;
+                       nbytes_frame += nbytes_fragment;
+
+                       memcpy(dest, (void *)dev.rx_dq.current->buffer_address,
+                                       nbytes_fragment);
+                       dest += nbytes_fragment;
+
+                       /* Clear the associated status queue entry, and
+                        * increment our current pointers to the next RX
+                        * descriptor and status queue entries (making sure
+                        * we wrap properly). */
+                       memset(dev.rx_sq.current, 0, sizeof(rx_status_t));
+
+                       dev.rx_sq.current++;
+                       if (dev.rx_sq.current >= dev.rx_sq.end)
+                               dev.rx_sq.current = dev.rx_sq.base;
+
+                       dev.rx_dq.current++;
+                       if (dev.rx_dq.current >= dev.rx_dq.end) {
+                               dev.rx_dq.current = dev.rx_dq.base;
+                       }
+
+                       /* Finally, return the RX descriptor and status entries
+                        * back to the MAC engine, and loop again, checking for
+                        * more descriptors to process. */
+                       OpReg_RxDEQ = 1;
+                       OpReg_RxSEQ = 1;
+
+               } else if (!dev.rx_sq.current->rfp && !dev.rx_sq.current->rwe) {
+                       /* We've no further queued descriptors.  If data have
+                        * been copied into the protocol layer, issue a
+                        * NetReceive() call to pass the data to the protocol
+                        * stack for further processing, and return
+                        * successfully. */
+                       if (nbytes_frame > 0) {
+                               NetReceive(NetRxPackets[0], nbytes_frame);
+                               TRACE(("reporting %d bytes (last: %d)...\n",
+                                               nbytes_frame, nbytes_fragment));
+                       }
+
+                       ret = ETH_STATUS_SUCCESS;
+                       break;
+
+               } else {
+                       /* Do we have an erroneous packet? */
+                       ERROR(("packet rx error, status %08X %08X",
+                                       dev.rx_sq.current->word1,
+                                       dev.rx_sq.current->word2));
+                       dump_rx_descriptor_queue();
+                       dump_rx_status_queue();
+
+                       /* TODO: Add better error handling? */
+                       break;
+               }
+       }
+
+       TRACE(("-eth_rx %d", ret));
+       return(ret);
+}
+
+
+/**
+ * Send a block of data via ethernet.
+ *
+ * TODO: Enhance this to deal with as much data as are available at one time?  */
+extern int eth_send(volatile void * const packet, int const length)
+{
+       int ret = ETH_STATUS_FAILURE;
+
+       TRACE(("+eth_send"));
+
+       /* Parameter check */
+       if (packet == NULL) {
+               ERROR(("NULL packet"));
+               goto eth_send_failed_0;
+       }
+
+       /* Initialize the TX descriptor queue with the new packet's info.
+        * Clear the associated status queue entry.  Enqueue the packet
+        * to the MAC for transmission. */
+       dev.tx_dq.current->buffer_address = (uint32_t)packet;
+       dev.tx_dq.current->buffer_length = length;
+       dev.tx_dq.current->buffer_index = 0;
+       dev.tx_dq.current->eof = 1;
+
+       dev.tx_sq.current->word1 = 0;
+
+       OpReg_TxDEQ = 1;
+
+       /* Wait for TX to complete, and check status entry for errors. */
+       while (!(OpReg_IntStsC & IntSts_TxStsQ)) {
+               /* nop */
+       }
+
+       if (!dev.tx_sq.current->txfp || !dev.tx_sq.current->txwe) {
+               ERROR(("packet tx error, status %08X",
+                               dev.tx_sq.current->word1));
+               dump_tx_descriptor_queue();
+               dump_tx_status_queue();
+
+               /* TODO: Add better error handling? */
+               goto eth_send_failed_0;
+       }
+
+       ret = ETH_STATUS_SUCCESS;
+       /* Fall through */
+
+eth_send_failed_0:
+       TRACE(("-eth_send %d", ret));
+       return(ret);
+}
+#endif  /* defined(CONFIG_DRIVER_EP93XX_MAC) */
+
+
+/* -----------------------------------------------------------------------------
+ * EP93xx ethernet MII functionality.
+ */
+#if defined(CONFIG_MII)
+
+/**
+ * Maximum MII address we support
+ */
+#define MII_ADDRESS_MAX                        (31)
+
+/**
+ * Maximum MII register address we support
+ */
+#define MII_REGISTER_MAX               (31)
+
+
+/**
+ * Ethernet MII interface return values for public functions.
+ */
+enum mii_status {
+       MII_STATUS_SUCCESS = 0,
+       MII_STATUS_FAILURE = 1,
+};
+
+
+/**
+ * Read a 16-bit value from an MII register.
+ */
+static int ep93xx_miiphy_read(char * const dev, unsigned char const addr,
+               unsigned char const reg, unsigned short * const value)
+{
+       int ret = MII_STATUS_FAILURE;
+       uint32_t self_ctl;
+
+       TRACE(("+ep93xx_miiphy_read"));
+
+       /* Parameter checks */
+       if (dev == NULL) {
+               ERROR(("NULL dev"));
+               goto ep93xx_miiphy_read_failed_0;
+       }
+
+       if (addr > MII_ADDRESS_MAX) {
+               ERROR(("invalid addr, 0x%02X", addr));
+               goto ep93xx_miiphy_read_failed_0;
+       }
+
+       if (reg > MII_REGISTER_MAX) {
+               ERROR(("invalid reg, 0x%02X", reg));
+               goto ep93xx_miiphy_read_failed_0;
+       }
+
+       if (value == NULL) {
+               ERROR(("NULL value"));
+               goto ep93xx_miiphy_read_failed_0;
+       }
+
+       /* Save the current SelfCTL register value.  Set MAC to suppress
+        * preamble bits.  Wait for any previous MII command to complete
+        * before issuing the new command. */
+       self_ctl = OpReg_SelfCTL;
+#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
+       OpReg_SelfCTL = (self_ctl & ~(1 << 8));
+#endif  /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
+
+       while (OpReg_MIISts & MIISts_Busy) {
+               /* nop */
+       }
+
+       /* Issue the MII 'read' command.  Wait for the command to complete.
+        * Read the MII data value. */
+       OpReg_MIICmd = (MIICmd_Opcode_Read | ((uint32_t)addr << 5) |
+                       (uint32_t)reg);
+       while (OpReg_MIISts & MIISts_Busy) {
+               /* nop */
+       }
+
+       *value = (unsigned short)OpReg_MIIData;
+
+       /* Restore the saved SelfCTL value and return. */
+       OpReg_SelfCTL = self_ctl;
+
+       ret = MII_STATUS_SUCCESS;
+       /* Fall through */
+
+ep93xx_miiphy_read_failed_0:
+       TRACE(("-ep93xx_miiphy_read"));
+       return(ret);
+}
+
+
+/**
+ * Write a 16-bit value to an MII register.
+ */
+static int ep93xx_miiphy_write(char * const dev, unsigned char const addr,
+               unsigned char const reg, unsigned short const value)
+{
+       int ret = MII_STATUS_FAILURE;
+       uint32_t self_ctl;
+
+       TRACE(("+ep93xx_miiphy_write"));
+
+       /* Parameter checks */
+       if (dev == NULL) {
+               ERROR(("NULL dev"));
+               goto ep93xx_miiphy_write_failed_0;
+       }
+
+       if (addr > MII_ADDRESS_MAX) {
+               ERROR(("invalid addr, 0x%02X", addr));
+               goto ep93xx_miiphy_write_failed_0;
+       }
+
+       if (reg > MII_REGISTER_MAX) {
+               ERROR(("invalid reg, 0x%02X", reg));
+               goto ep93xx_miiphy_write_failed_0;
+       }
+
+       /* Save the current SelfCTL register value.  Set MAC to suppress
+        * preamble bits.  Wait for any previous MII command to complete
+        * before issuing the new command. */
+       self_ctl = OpReg_SelfCTL;
+#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
+       OpReg_SelfCTL = (self_ctl & ~(1 << 8));
+#endif  /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
+
+       while (OpReg_MIISts & MIISts_Busy) {
+               /* nop */
+       }
+
+       /* Issue the MII 'write' command.  Wait for the command to complete. */
+       OpReg_MIIData = (uint32_t)value;
+       OpReg_MIICmd = (MIICmd_Opcode_Write | ((uint32_t)addr << 5) |
+                       (uint32_t)reg);
+       while (OpReg_MIISts & MIISts_Busy) {
+               /* nop */
+       }
+
+       /* Restore the saved SelfCTL value and return. */
+       OpReg_SelfCTL = self_ctl;
+
+       ret = MII_STATUS_SUCCESS;
+       /* Fall through */
+
+ep93xx_miiphy_write_failed_0:
+       TRACE(("-ep93xx_miiphy_write"));
+       return(ret);
+}
+#endif  /* defined(CONFIG_MII) */
+
Index: u-boot/cpu/arm920t/ep93xx/Makefile
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ u-boot/cpu/arm920t/ep93xx/Makefile	2007-09-23 13:50:11.000000000 +0200
@@ -0,0 +1,48 @@
+# vim: set ts=8 sw=8 noet:
+#
+# Cirrus Logic EP93xx CPU-specific Makefile
+#
+# Copyright (C) 2004, 2005
+# Cory T. Tusar, Videon Central, Inc., <ctusar@xxxxxxxxxxxxxxxxxx>
+#
+# Based on an original Makefile, which is
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@xxxxxxxx
+#
+# See file CREDITS for list of people who contributed to this project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+# for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+include $(TOPDIR)/config.mk
+
+LIB   = $(obj)lib$(SOC).a
+COBJS = cpu.o eth.o interrupts.o speed.o
+SRCS  := $(COBJS:.o=.c)
+OBJS  := $(addprefix $(obj),$(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
Index: u-boot/cpu/arm920t/ep93xx/speed.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ u-boot/cpu/arm920t/ep93xx/speed.c	2007-09-23 12:41:23.000000000 +0200
@@ -0,0 +1,83 @@
+/* vim: set ts=8 sw=8 noet:
+ *
+ * Cirrus Logic EP93xx PLL support.
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@xxxxxxxxxxxxxxxxxx>
+ *
+ * Based on the S3C24x0 speed.c, which is
+ *
+ * (C) Copyright 2001-2002
+ * Wolfgang Denk, DENX Software Engineering, <wd@xxxxxxx>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@xxxxxxxxx>
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <common.h>
+#include <ep93xx.h>
+
+