u-boot-1.2.0-edb93xx_support.diff

u-boot 1.2.0 for ep93

+                       unsigned ow             :  1;
+                       unsigned                :  1;
+                       unsigned lcrs           :  1;
+                       unsigned fa             :  1;
+                       unsigned txwe           :  1;
+                       unsigned txfp           :  1;
+               };
+       };
+} __attribute__((packed));
+
+typedef struct tx_status_t tx_status_t;
+
+
+/**
+ * Transmit descriptor queue
+ */
+struct tx_descriptor_queue_t {
+       tx_descriptor_t *base;
+       tx_descriptor_t *current;
+       tx_descriptor_t *end;
+};
+
+typedef struct tx_descriptor_queue_t tx_descriptor_queue_t;
+
+
+/**
+ * Transmit status queue
+ */
+struct tx_status_queue_t {
+       tx_status_t *base;
+       tx_status_t *current;
+       tx_status_t *end;
+};
+
+typedef struct tx_status_queue_t tx_status_queue_t;
+
+
+/**
+ * Receive descriptor queue
+ */
+struct rx_descriptor_queue_t {
+       rx_descriptor_t *base;
+       rx_descriptor_t *current;
+       rx_descriptor_t *end;
+};
+
+typedef struct rx_descriptor_queue_t rx_descriptor_queue_t;
+
+
+/**
+ * Receive status queue
+ */
+struct rx_status_queue_t {
+       rx_status_t *base;
+       rx_status_t *current;
+       rx_status_t *end;
+};
+
+typedef struct rx_status_queue_t rx_status_queue_t;
+
+
+/**
+ * EP93xx MAC private data structure
+ */
+struct ep93xx_mac {
+       int                     is_initialized;
+
+       rx_descriptor_queue_t   rx_dq;
+       rx_status_queue_t       rx_sq;
+       void *                  rx_buffer[NUMRXDESC];
+
+       tx_descriptor_queue_t   tx_dq;
+       tx_status_queue_t       tx_sq;
+};
+
+
+/* ep93xx_miiphy ops forward declarations */
+static int ep93xx_miiphy_read(char * const dev, unsigned char const addr,
+               unsigned char const reg, unsigned short * const value);
+static int ep93xx_miiphy_write(char * const dev, unsigned char const addr,
+               unsigned char const reg, unsigned short const value);
+
+
+/* Reserve memory for the MAC's private data */
+static struct ep93xx_mac dev = { 0 };
+
+
+/**
+ * Dump ep93xx_mac values to the terminal.
+ */
+extern inline void dump_dev(void)
+{
+#if defined(EP93XX_MAC_DEBUG)
+       int i;
+
+       printf("\ndump_dev()\n");
+       printf("  is_initialized     %02X\n", dev.is_initialized);
+       printf("  rx_dq.base         %08X\n", dev.rx_dq.base);
+       printf("  rx_dq.current      %08X\n", dev.rx_dq.current);
+       printf("  rx_dq.end          %08X\n", dev.rx_dq.end);
+       printf("  rx_sq.base         %08X\n", dev.rx_sq.base);
+       printf("  rx_sq.current      %08X\n", dev.rx_sq.current);
+       printf("  rx_sq.end          %08X\n", dev.rx_sq.end);
+
+       for (i = 0; i < NUMRXDESC; i++) {
+               printf("  rx_buffer[%2.d]      %08X\n", i, dev.rx_buffer[i]);
+       }
+
+       printf("  tx_dq.base         %08X\n", dev.tx_dq.base);
+       printf("  tx_dq.current      %08X\n", dev.tx_dq.current);
+       printf("  tx_dq.end          %08X\n", dev.tx_dq.end);
+       printf("  tx_sq.base         %08X\n", dev.tx_sq.base);
+       printf("  tx_sq.current      %08X\n", dev.tx_sq.current);
+       printf("  tx_sq.end          %08X\n", dev.tx_sq.end);
+#endif  /* defined(EP93XX_MAC_DEBUG) */
+}
+
+
+/**
+ * Dump all RX descriptor queue entries to the terminal.
+ */
+extern inline void dump_rx_descriptor_queue(void)
+{
+#if defined(EP93XX_MAC_DEBUG)
+       int i;
+
+       printf("\ndump_rx_descriptor_queue()\n");
+       printf("  descriptor address     word1           word2\n");
+       for (i = 0; i < NUMRXDESC; i++) {
+               printf("  [ %08X ]           %08X        %08X\n",
+                               (dev.rx_dq.base + i),
+                               (dev.rx_dq.base + i)->word1,
+                               (dev.rx_dq.base + i)->word2);
+       }
+#endif  /* defined(EP93XX_MAC_DEBUG) */
+}
+
+
+/**
+ * Dump all RX status queue entries to the terminal.
+ */
+extern inline void dump_rx_status_queue(void)
+{
+#if defined(EP93XX_MAC_DEBUG)
+       int i;
+
+       printf("\ndump_rx_status_queue()\n");
+       printf("  descriptor address     word1           word2\n");
+       for (i = 0; i < NUMRXDESC; i++) {
+               printf("  [ %08X ]           %08X        %08X\n",
+                               (dev.rx_sq.base + i),
+                               (dev.rx_sq.base + i)->word1,
+                               (dev.rx_sq.base + i)->word2);
+       }
+#endif  /* defined(EP93XX_MAC_DEBUG) */
+}
+
+
+/**
+ * Dump all TX descriptor queue entries to the terminal.
+ */
+extern inline void dump_tx_descriptor_queue(void)
+{
+#if defined(EP93XX_MAC_DEBUG)
+       int i;
+
+       printf("\ndump_tx_descriptor_queue()\n");
+       printf("  descriptor address     word1           word2\n");
+       for (i = 0; i < NUMTXDESC; i++) {
+               printf("  [ %08X ]           %08X        %08X\n",
+                               (dev.tx_dq.base + i),
+                               (dev.tx_dq.base + i)->word1,
+                               (dev.tx_dq.base + i)->word2);
+       }
+#endif  /* defined(EP93XX_MAC_DEBUG) */
+}
+
+
+/**
+ * Dump all TX status queue entries to the terminal.
+ */
+extern inline void dump_tx_status_queue(void)
+{
+#if defined(EP93XX_MAC_DEBUG)
+       int i;
+
+       printf("\ndump_tx_status_queue()\n");
+       printf("  descriptor address     word1\n");
+       for (i = 0; i < NUMTXDESC; i++) {
+               printf("  [ %08X ]           %08X\n",
+                               (dev.rx_sq.base + i),
+                               (dev.rx_sq.base + i)->word1);
+       }
+#endif  /* defined(EP93XX_MAC_DEBUG) */
+}
+
+
+/**
+ * Reset the EP93xx MAC by twiddling the soft reset bit and spinning until
+ * it's cleared.
+ */
+static void ep93xx_mac_reset(void)
+{
+       TRACE(("+ep93xx_mac_reset"));
+
+       OpReg_SelfCTL |= SelfCTL_RESET;
+       while (OpReg_SelfCTL & SelfCTL_RESET) {
+               /* nop */
+       }
+
+       TRACE(("-ep93xx_mac_reset"));
+}
+
+
+/**
+ * Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL
+ * registers.
+ */
+extern void eth_halt(void)
+{
+       TRACE(("+eth_halt"));
+
+       OpReg_RxCTL = 0x00000000;
+       OpReg_TxCTL = 0x00000000;
+
+       TRACE(("-eth_halt"));
+}
+
+
+/**
+ * Initialize the EP93xx MAC.  The MAC hardware is reset.  Buffers are
+ * allocated, if necessary, for the TX and RX descriptor and status queues,
+ * as well as for received packets.  The EP93XX MAC hardware is initialized.
+ * Transmit and receive operations are enabled.
+ */
+extern int eth_init(bd_t * const bd)
+{
+       int ret = ETH_STATUS_FAILURE;
+       int i;
+       int need_miireg = 0;
+
+       TRACE(("+eth_init"));
+
+       /* Parameter check */
+       if (bd == NULL) {
+               ERROR(("NULL bd"));
+               goto eth_init_failed_0;
+       }
+
+       /* Reset the MAC */
+       ep93xx_mac_reset();
+
+       /* Allocate space for the queues and RX packet buffers if we're not
+        * already initialized */
+       if (!dev.is_initialized) {
+               if ((dev.tx_dq.base = calloc(NUMTXDESC,
+                                       sizeof(tx_descriptor_t))) == NULL) {
+                       ERROR(("calloc() failed"));
+                       goto eth_init_failed_0;
+               }
+
+               if ((dev.tx_sq.base = calloc(NUMTXDESC,
+                                       sizeof(tx_status_t))) == NULL) {
+                       ERROR(("calloc() failed"));
+                       goto eth_init_failed_1;
+               }
+
+               if ((dev.rx_dq.base = calloc(NUMRXDESC,
+                                       sizeof(rx_descriptor_t))) == NULL) {
+                       ERROR(("calloc() failed"));
+                       goto eth_init_failed_2;
+               }
+
+               if ((dev.rx_sq.base = calloc(NUMRXDESC,
+                                       sizeof(rx_status_t))) == NULL) {
+                       ERROR(("calloc() failed"));
+                       goto eth_init_failed_3;
+               }
+
+               for (i = 0; i < NUMRXDESC; i++) {
+                       dev.rx_buffer[i] = NULL;
+               }
+
+               for (i = 0; i < NUMRXDESC; i++) {
+                       if ((dev.rx_buffer[i] = calloc(1, PKTSIZE)) == NULL) {
+                               ERROR(("calloc() failed"));
+                               goto eth_init_failed_4;
+                       }
+               }
+
+               /* Set is_initialized flag so we don't go through allocation
+                * portion of init again. */
+               dev.is_initialized = 1;
+               need_miireg = 1;
+       }
+
+       /* Reset the descriptor queues' current and end address values */
+       dev.tx_dq.current = dev.tx_dq.base;
+       dev.tx_dq.end = (dev.tx_dq.base + NUMTXDESC);
+
+       dev.tx_sq.current = dev.tx_sq.base;
+       dev.tx_sq.end = (dev.tx_sq.base + NUMTXDESC);
+
+       dev.rx_dq.current = dev.rx_dq.base;
+       dev.rx_dq.end = (dev.rx_dq.base + NUMRXDESC);
+
+       dev.rx_sq.current = dev.rx_sq.base;
+       dev.rx_sq.end = (dev.rx_sq.base + NUMRXDESC);
+
+       /* Set the transmit descriptor and status queues' base address,
+        * current address, and length registers.  Set the maximum frame
+        * length and threshold.  Enable the transmit descriptor processor. */
+       OpReg_TxDBA = (uint32_t)dev.tx_dq.base;
+       OpReg_TxDCA = (uint32_t)dev.tx_dq.base;
+       OpReg_TxDBL = (sizeof(tx_descriptor_t) * NUMTXDESC);
+
+       OpReg_TxSBA = (uint32_t)dev.tx_sq.base;
+       OpReg_TxSCA = (uint32_t)dev.tx_sq.base;
+
+       OpReg_TxDTH = 0x00040000;
+
+       OpReg_TxSBL = (sizeof(tx_status_t) * NUMTXDESC);
+
+       OpReg_TxSTH = 0x00040000;
+
+
+       OpReg_MaxFL = (TXSTARTMAX << 16) | (PKTSIZE << 0);
+       OpReg_BMCTL = BMCTL_TxEn;
+
+       /* Set the receive descriptor and status queues' base address,
+        * current address, and length registers.  Enable the receive
+        * descriptor processor. */
+       OpReg_RxDBA = (uint32_t)dev.rx_dq.base;
+       OpReg_RxDCA = (uint32_t)dev.rx_dq.base;
+       OpReg_RxDBL = (sizeof(rx_descriptor_t) * NUMRXDESC);
+
+       OpReg_RxSBA = (uint32_t)dev.rx_sq.base;
+       OpReg_RxSCA = (uint32_t)dev.rx_sq.base;
+       OpReg_RxSBL = (sizeof(rx_status_t) * NUMRXDESC);
+
+       OpReg_RxDTH = 0x00040000;
+
+       OpReg_BMCTL = BMCTL_RxEn;
+
+       OpReg_RxSTH = 0x00040000;
+
+       /* Wait until the receive descriptor processor is active */
+       while (!(OpReg_BMSts & BMSts_RxAct)) {
+               /* nop */
+       }
+
+       /* Initialize the RX descriptor queue.  Clear the TX descriptor queue.
+        * Clear the RX and TX status queues.  Enqueue the RX descriptor and
+        * status entries to the MAC. */
+       for (i = 0; i < NUMRXDESC; i++) {
+               (dev.rx_dq.base + i)->buffer_address =
+                       (uint32_t)dev.rx_buffer[i];
+               (dev.rx_dq.base + i)->buffer_length = PKTSIZE;
+               (dev.rx_dq.base + i)->buffer_index = 0;
+       }
+
+       memset(dev.tx_dq.base, 0, (sizeof(tx_descriptor_t) * NUMTXDESC));
+       memset(dev.rx_sq.base, 0, (sizeof(rx_status_t) * NUMRXDESC));
+       memset(dev.tx_sq.base, 0, (sizeof(tx_status_t) * NUMTXDESC));
+
+       OpReg_RxDEQ = NUMRXDESC;
+       OpReg_RxSEQ = NUMRXDESC;
+
+       /* Set the primary MAC address */
+       OpReg_AFP = AFP_IAPrimary;
+       OpReg_IndAd = (bd->bi_enetaddr[0] |
+                       (bd->bi_enetaddr[1] << 8) |
+                       (bd->bi_enetaddr[2] << 16) |
+                       (bd->bi_enetaddr[3] << 24));
+       OpReg_IndAd1 = (bd->bi_enetaddr[4] | (bd->bi_enetaddr[5] << 8));
+
+       /* Turn on RX and TX */
+       OpReg_RxCTL = (RxCTL_IndividualAccept0 | RxCTL_BroadcastA |
+                       RxCTL_SerRxON | RxCTL_RuntCRCA | RxCTL_MulticastA);
+       OpReg_TxCTL = TxCTL_SerTxON;
+
+       /* Dump data structures if we're debugging */
+       dump_dev();
+       dump_rx_descriptor_queue();
+       dump_rx_status_queue();
+       dump_tx_descriptor_queue();
+       dump_tx_status_queue();
+
+#if defined(CONFIG_MII)
+       if (need_miireg) miiphy_register("ep93xx_eth0", ep93xx_miiphy_read, ep93xx_miiphy_write);
+#endif
+
+       /* Done! */
+       ret = ETH_STATUS_SUCCESS;
+       goto eth_init_done;
+
+eth_init_failed_4:
+       for (i = 0; i < NUMRXDESC; i++) {
+               if (dev.rx_buffer[i] != NULL) {
+                       free(dev.rx_buffer[i]);
+               }
+       }
+