u-boot-1.2.0-edb93xx_support.diff

u-boot 1.2.0 for ep93

based on edb93xx support patch from linux-cirrus mailing list,
http://www.freelists.org/archives/linux-cirrus/04-2006/msg00008.html,
with following tweaks:

 - forward ported to u-boot 1.2
 - ep93xx cpu detection:
   * dump id registers used for detecting cpu type on bootup
   * added magic values for EP9307 rev. E1 and E2
 - fix memory setup on edb9307 (and maybe ep9312/15 as well)
 - improve tftp timeouts in u-boot by implementing errata (http://www.freelists.org/archives/linux-cirrus/12-2005/msg00004.html)
 - call miiphy_register() only once
 - configure UARTs like cirrus' redboot
 - various cleanups
 - some bits from the patch http://ml.osdir.com/linux.ports.arm.cirrus/2006-11/msg00009.html:
   * place "CRUS" magic at 0x1000 instead of 0x0
   * reuse `drivers/serial_pl010.c` instead of providing own implementation in `ep93xx/serial.c`

TODO:
 - perform PLL setup at sdram config time (i.e. prior to relocation to sdram) 
 - review PLL settings
 - implement stubs in `speed.c`
 - set fullduplex bit in TestCTL depending on PHY link state

Index: u-boot/board/edb93xx/config.mk
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ u-boot/board/edb93xx/config.mk	2007-09-23 13:01:35.000000000 +0200
@@ -0,0 +1,17 @@
+#
+# (C) Copyright 2002-2003
+# Adam Bezanson, Network Audio Technologies, Inc., <bezanson@xxxxxxxxxxxxxxxx>
+#
+# Cirrus Logic board for Cirrus Logic EP9312 Rev D. (ARM920T) cpu
+#
+#
+#
+##################################################
+# Assumed configuration for EDB9312 revision 2
+# Internal boot
+# SDRAM chip select: /SDCS3
+# SDRAM size: 64 MiB
+# Sync Memory Boot
+#
+# We place the stuff close to the SDRAM upper bound of the first 32MiB
+TEXT_BASE = 0x01f00000
Index: u-boot/board/edb93xx/edb93xx.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ u-boot/board/edb93xx/edb93xx.c	2007-09-23 14:31:40.000000000 +0200
@@ -0,0 +1,209 @@
+/*
+ * (C) Copyright 2002 2003
+ * Network Audio Technologies, Inc. <www.netaudiotech.com>
+ * Adam Bezanson <bezanson@xxxxxxxxxxxxxxxx>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ep93xx.h>
+#include <linux/byteorder/swab.h>
+
+#define HAL_WRITE_UINT32( _register_, _value_ ) \
+        (*((volatile u32 *)(_register_)) = (_value_))
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	u32 ClkSet1;
+	u32 ClkSet2;
+
+	/* PLL frequency calculation:
+	 *
+	 * PLLn FOUT = 14.7456 MHz *  (PLLn_X1FBD1+1)*(PLLn_X2FBD2+1)
+	 *                         /( (PLLn_X2IPD+1)*(1<<PLLn_X2IPD) )
+	 */
+
+	//
+	// configure PLL2
+	//
+	ClkSet2 = (EP9312_CLKSET2_NBYP2
+		   | EP9312_CLKSET2_PLL2_EN
+		   | (24 << EP9312_CLKSET2_PLL2_X1FBD1_SHIFT)
+		   | (24 << EP9312_CLKSET2_PLL2_X2FBD2_SHIFT)
+		   | (23 << EP9312_CLKSET2_PLL2_X2IPD_SHIFT));
+
+	/* PLL2 FOUT=192MHz
+	 * ClkSet2 |= (1 << EP9312_CLKSET2_PLL2_PS_SHIFT);
+	 * ClkSet2 |= (3 << EP9312_CLKSET2_USB_DIV_SHIFT);
+	 */
+
+	// PLL2 FOUT=384MHz
+	ClkSet2 |= (0 << EP9312_CLKSET2_PLL2_PS_SHIFT);
+	ClkSet2 |= (7 << EP9312_CLKSET2_USB_DIV_SHIFT);
+
+#ifdef CONFIG_EP9301
+	//
+	// Set the output of the PLL1 to 332Mhz
+	//
+	ClkSet1 = (EP9312_CLKSET1_NBYP1
+		   | (31 << EP9312_CLKSET1_PLL1_X1FBD1_SHIFT)
+		   | (18 << EP9312_CLKSET1_PLL1_X2FBD2_SHIFT)
+		   | (26 << EP9312_CLKSET1_PLL1_X2IPD_SHIFT));
+
+	//
+	// Set the FCLKDIV value to divide by 2 (166Mhz).
+	//
+	ClkSet1 |= (1 << EP9312_CLKSET1_FCLKDIV_SHIFT);
+
+	//
+	// Set the HCLKDIV value to divide by 5 (66Mhz).
+	//
+	ClkSet1 |= (3 << EP9312_CLKSET1_HCLKDIV_SHIFT);
+#else
+	//
+	// Set the output of the PLL to 400Mhz
+	//
+	ClkSet1 = (EP9312_CLKSET1_NBYP1
+		   | (28 << EP9312_CLKSET1_PLL1_X1FBD1_SHIFT)
+		   | (28 << EP9312_CLKSET1_PLL1_X2FBD2_SHIFT)
+		   | (30 << EP9312_CLKSET1_PLL1_X2IPD_SHIFT));
+
+	//
+	// Set the FCLK to 400/2 or 200Mhz
+	//
+	ClkSet1 |= (1 << EP9312_CLKSET1_FCLKDIV_SHIFT);
+
+	//
+	// Set the HCLK to 400/4 or 100Mhz
+	//
+	ClkSet1 |= (2 << EP9312_CLKSET1_HCLKDIV_SHIFT);
+#endif // CONFIG_EP9301
+
+	//
+	// Set PCLKDIV so that PCLK = HCLK / 2
+	//
+	ClkSet1 |= (1 << EP9312_CLKSET1_PCLKDIV_SHIFT);
+
+	// set ClkSet1 register
+	HAL_WRITE_UINT32(EP9312_CLKSET1, ClkSet1);
+
+	//
+	// Do the five required nops to keep us clean.
+	//
+	__asm("nop");
+	__asm("nop");
+	__asm("nop");
+	__asm("nop");
+	__asm("nop");
+
+	//
+	// Write out the value to ClkSet 2
+	//
+	HAL_WRITE_UINT32(EP9312_CLKSET2, ClkSet2);
+
+	//
+	// Go to Async mode
+	//
+	__asm("mrc p15, 0, r0, c1, c0, 0");
+	__asm("orr r0, r0, #0xc0000000");
+	__asm("mcr p15, 0, r0, c1, c0, 0");
+
+	icache_enable();
+
+#ifdef USE_920T_MMU
+	dcache_enable();
+#endif
+
+	//
+	// TODO remove this hack.  This is to set the wait states to max for Flash.
+	//
+#ifdef CONFIG_EP9301
+	SMC_BCR6 = 0x1000ffef;
+#else
+	SMC_BCR6 = 0x2000ffef;
+#endif // CONFIG_EP9301
+
+	//
+	// Set this bit like the Kernel expects it (runs serial off of the 14Mhz).
+	//
+	HAL_WRITE_UINT32(EP9312_PWRCNT, EP9312_PWRCNT_UARTBAUD);
+
+        const u32 syscon = SysconDEVCFG;
+        SYSCON_SW_UNCLOCK;
+        SysconDEVCFG = syscon | EP9312_DEVCFG_U1EN;
+
+	/* Machine number, as defined in linux/arch/arm/tools/mach-types */
+	/* #define MACH_TYPE_EDB9312              451
+	 * #define MACH_TYPE_EDB9301              462
+	 * #define MACH_TYPE_EDB9315              463
+	 * #define MACH_TYPE_EDB9302              538
+	 * #define MACH_TYPE_EDB9307              607
+	 */
+#if defined(CONFIG_EDB9301)
+	gd->bd->bi_arch_number = MACH_TYPE_EDB9301;
+#elif defined(CONFIG_EDB9302)
+	gd->bd->bi_arch_number = MACH_TYPE_EDB9302;
+#elif defined(CONFIG_EDB9307)
+	gd->bd->bi_arch_number = MACH_TYPE_EDB9307;
+#elif defined(CONFIG_EDB9312)
+	gd->bd->bi_arch_number = MACH_TYPE_EDB9312;
+#elif defined(CONFIG_EDB9315)
+	gd->bd->bi_arch_number = MACH_TYPE_EDB9315;
+#else
+#error "CONFIG_EDB93nn is not properly #define'd"
+#endif
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
+
+	/* We have a console */
+	gd->have_console = 1;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+#if CONFIG_NR_DRAM_BANKS>0
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE_1;
+#else
+# error bad bank config
+#endif
+
+#if CONFIG_NR_DRAM_BANKS>1
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_SIZE_2;
+#endif
+
+#if CONFIG_NR_DRAM_BANKS>2
+# error bad bank config
+#endif
+
+	return 0;
+}
Index: u-boot/board/edb93xx/Makefile
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ u-boot/board/edb93xx/Makefile	2007-09-23 12:41:23.000000000 +0200
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@xxxxxxxx
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS  := edb93xx.o
+SOBJS  := lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+all:   $(HDR) $(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
Index: u-boot/board/edb93xx/sdramcfg.S
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ u-boot/board/edb93xx/sdramcfg.S	2007-09-23 12:41:23.000000000 +0200
@@ -0,0 +1,198 @@
+/*=============================================================================
+//
+//      sdramcfg.h
+//
+//      SDRAM Configuration Routine.
+//
+//=============================================================================
+//####COPYRIGHTBEGIN####
+//
+// -------------------------------------------
+// Copyright(c) Cirrus Logic Corporation 2003, All Rights Reserved
+// -------------------------------------------
+//
+//####COPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jordan
+// Contributors: rgorsegn
+// Date:         2003-08-15
+// Purpose:      Cirrus Logic EP93xx SDRAM Config Routine
+// Description:
+// Usage:        #include <cyg/hal/sdramcfg.h>
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#define GLOBALCFG_INIT                       0x00000001
+#define GLOBALCFG_MRS                        0x00000002
+#define GLOBALCFG_SMEMBUSY                   0x00000020
+#define GLOBALCFG_LCR                        0x00000040
+#define GLOBALCFG_REARBEN                    0x00000080
+#define GLOBALCFG_CLKSHUTDOWN                0x40000000
+#define GLOBALCFG_CKE                        0x80000000
+
+#define REFRESH_MASK                         0x0000FFFF
+
+#define BOOTSTATUS_WIDTH_32                  0x00000002
+#define BOOTSTATUS_WIDTH_16                  0x00000001
+#define BOOTSTATUS_WIDTH_8                   0x00000000
+#define BOOTSTATUS_WIDTH_MASK                0x00000003
+#define BOOTSTATUS_MEDIA                     0x00000004
+
+#define DEVCFG_EXTBUSWIDTH                   0x00000004
+#define DEVCFG_BANKCOUNT                     0x00000008
+#define DEVCFG_SROM512                       0x00000010
+#define DEVCFG_SROMLL                        0x00000020
+#define DEVCFG_2KPAGE                        0x00000040
+#define DEVCFG_SFCONFIGADDR                  0x00000080
+#define DEVCFG_CASLAT_MASK                   0x00070000
+#define DEVCFG_CASLAT_2                      0x00010000
+#define DEVCFG_CASLAT_3                      0x00020000
+#define DEVCFG_CASLAT_4                      0x00030000
+#define DEVCFG_CASLAT_5                      0x00040000
+#define DEVCFG_CASLAT_6                      0x00050000
+#define DEVCFG_CASLAT_7                      0x00060000
+#define DEVCFG_CASLAT_8                      0x00070000
+#define DEVCFG_WBL                           0x00080000
+#define DEVCFG_RASTOCAS_MASK                 0x00300000
+#define DEVCFG_RASTOCAS_2                    0x00200000
+#define DEVCFG_RASTOCAS_3                    0x00300000
+#define DEVCFG_AUTOPRECHARGE                 0x01000000
+
+//****************************************************************************
+// Delay200 - Delays200 us
+//
+//   Uses    r0
+//****************************************************************************
+    .macro Delay200
+    mov     r0, #64
+200:
+    subs    r0, r0, #1
+    bne     200b
+    .endm
+
+//****************************************************************************
+// SdramCfg - Initialize SDRAM controller
+//
+//   Uses    r0