mem.s

基于华邦W90P710 arm开发板的AC97模块测试程序

;******************************************************	
;System memory define
;******************************************************  

Mode_USR        EQU	0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UNDEF      EQU     0x1B
Mode_SYS        EQU     0x1F ; available on ARM Arch 4 and later
Mask_MODE       EQU     0x3F

I_Bit           EQU     0x80 ; when I bit is set, IRQ is disabled
F_Bit           EQU     0x40 ; when F bit is set, FIQ is disabled

EBI_Ctrl		EQU		0xFFF01000			; W90P710 EBI Controle register


RAM_Limit       EQU     0x8000          	; For unexpanded W90P710 board

UND_Stack		EQU		RAM_Limit
Abort_Stack		EQU		RAM_Limit-256
IRQ_Stack       EQU     RAM_Limit-512       ; followed by IRQ stack
FIQ_Stack       EQU     RAM_Limit-768       ; followed by IRQ stack
SVC_Stack       EQU     RAM_Limit-1024      ; SVC stack at top of memory
USR_Stack       EQU     0x7000	       ; followed by USR(SYS) stack


;******************************************************	
;aic registers define
;******************************************************  
AIC_BA			EQU		0xFFF82000     ;the start address of aic registers
      
AIC_SCR1		EQU		AIC_BA+0x04    ; Source control register 1 
AIC_SCR2		EQU		AIC_BA+0x08    ; Source control register 2 
AIC_SCR3     	EQU		AIC_BA+0x0C    ; Source control register 3 
AIC_SCR4     	EQU 	AIC_BA+0x10    ; Source control register 4 
AIC_SCR5		EQU 	AIC_BA+0x14    ; Source control register 5 
AIC_SCR6		EQU 	AIC_BA+0x18    ; Source control register 6 
AIC_SCR7		EQU 	AIC_BA+0x1C    ; Source control register 7 
AIC_SCR8     	EQU 	AIC_BA+0x20    ; Source control register 8 
AIC_SCR9     	EQU 	AIC_BA+0x24    ; Source control register 9 
AIC_SCR10    	EQU 	AIC_BA+0x28    ; Source control register 10 
AIC_SCR11   	EQU 	AIC_BA+0x2C    ; Source control register 11 
AIC_SCR12		EQU		AIC_BA+0x30    ; Source control register 12 
AIC_SCR13   	EQU 	AIC_BA+0x34    ; Source control register 13 
AIC_SCR14   	EQU 	AIC_BA+0x38    ; Source control register 14 
AIC_SCR15   	EQU 	AIC_BA+0x3C    ; Source control register 15 
AIC_SCR16   	EQU 	AIC_BA+0x40    ; Source control register 16 
AIC_SCR17   	EQU 	AIC_BA+0x44    ; Source control register 17 
AIC_SCR18   	EQU 	AIC_BA+0x48    ; Source control register 18 
AIC_SCR19   	EQU 	AIC_BA+0x4C    ; Source control register 19 
AIC_SCR20   	EQU		AIC_BA+0x50    ; Source control register 20 
AIC_SCR21   	EQU 	AIC_BA+0x54    ; Source control register 21 
AIC_SCR22		EQU 	AIC_BA+0x58    ; Source control register 22 
AIC_SCR23		EQU 	AIC_BA+0x5C    ; Source control register 23 
AIC_SCR24   	EQU 	AIC_BA+0x60    ; Source control register 24 
AIC_SCR25   	EQU 	AIC_BA+0x64    ; Source control register 25 
AIC_SCR26   	EQU 	AIC_BA+0x68    ; Source control register 26 
AIC_SCR27   	EQU 	AIC_BA+0x6c    ; Source control register 27 
AIC_SCR28   	EQU 	AIC_BA+0x70    ; Source control register 28 
AIC_SCR29   	EQU 	AIC_BA+0x74    ; Source control register 29 
AIC_SCR30   	EQU 	AIC_BA+0x78    ; Source control register 30 
AIC_SCR31   	EQU 	AIC_BA+0x7c    ; Source control register 31 

AIC_IRSR    	EQU 	AIC_BA+0x100   ; Interrupt raw status register 
AIC_IASR    	EQU 	AIC_BA+0x104   ; Interrupt active status register 
AIC_ISR     	EQU 	AIC_BA+0x108   ; Interrupt status register 
AIC_IPER    	EQU 	AIC_BA+0x10C   ; Interrupt priority encoding register 
AIC_ISNR    	EQU 	AIC_BA+0x110   ; Interrupt source number register 
AIC_IMR     	EQU 	AIC_BA+0x114   ; Interrupt mask register 
AIC_OISR    	EQU 	AIC_BA+0x118   ; Output interrupt status register 
AIC_MECR    	EQU 	AIC_BA+0x120   ; Mask enable command register 
AIC_MDCR    	EQU 	AIC_BA+0x124   ; Mask disable command register 
AIC_SSCR    	EQU 	AIC_BA+0x128   ; Source set command register 
AIC_SCCR    	EQU 	AIC_BA+0x12C   ; Source clear command register 
AIC_EOSCR   	EQU 	AIC_BA+0x130   ; End of service command register 
AIC_TEST    	EQU 	AIC_BA+0x200   ; ICE/Debug mode register


;******************************************************	
;GPIO registers define
;******************************************************  
GPIO_CFG5           EQU		0xFFF83050     ;configure regester       
GPIO_DIR5           EQU		0xFFF83054     ;direction regester
GPIO_DATAOUT5       EQU		0xFFF83058     ;data output regester
GPIO_DATAIN5        EQU		0xFFF8305C     ;data input  regester




;**************************************************************************************
  END