init.s

基于华邦W90P710 arm开发板的AC97模块测试程序

;*****************************************************************************
;* File Name		: init.s
;* Author			: 
;* Date				:
;* Version			: 
;* Description		: 初始化堆栈指针，使能中断，进入main()
;*****************************************************************************
;******************************************************	
;System memory define
;******************************************************  

Mode_USR		EQU		0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UNDEF      EQU     0x1B
Mode_SYS        EQU     0x1F ; available on ARM Arch 4 and later

I_Bit           EQU     0x80 ; when I bit is set, IRQ is disabled
F_Bit           EQU     0x40 ; when F bit is set, FIQ is disabled

EBI_Ctrl		EQU		0xFFF01000			; W90P710 EBI Controle register


RAM_Limit       EQU     0xffe02000          	; For unexpanded W90P710 board

UND_Stack		EQU		RAM_Limit
Abort_Stack		EQU		RAM_Limit-256
IRQ_Stack       EQU     RAM_Limit-512       ; followed by IRQ stack
FIQ_Stack       EQU     RAM_Limit-768       ; followed by IRQ stack
SVC_Stack       EQU     RAM_Limit-1024      ; SVC stack at top of memory
USR_Stack       EQU     0xffe01000	        ; followed by USR(SYS) stack

		EXPORT	Reset_Handler
        AREA    Init, CODE, READONLY

Reset_Handler
;******************************************************	
;Disable all interrupt
;******************************************************
		MRS		r0, CPSR
		ORR		r0, r0, #0xC0
		MSR		CPSR_c, r0

;******************************************************	
;Initialise stack pointer registers
;******************************************************
        MSR     CPSR_c, #Mode_UNDEF:OR:I_Bit:OR:F_Bit
        LDR     SP, =UND_Stack

        MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit 
        LDR     SP, =Abort_Stack

        MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
        LDR     SP, =IRQ_Stack

        MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
        LDR     SP, =FIQ_Stack

        MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
        LDR     SP, =SVC_Stack
       
        MSR     CPSR_c, #Mode_SYS:OR:I_Bit:OR:F_Bit
        LDR     SP, =USR_Stack


;******************************************************	
;Enable all interrupt
;******************************************************        
        MRS		r0, CPSR 
        BIC		r0, r0, #0xC0
        MSR 	CPSR_c, r0

		MSR     CPSR_c, #Mode_USR
		
		
		IMPORT	__main
		BL		__main
		B		.

		
		END