ex2_3.v

来自「精通VerilogHDL：IC设计核心技术实例详解」· Verilog 代码 · 共 25 行

module ex2_3;
//test bench
reg clk=0;
reg [2:0]in=0;
always #10 clk=~clk;
integer seed=4;
always@(posedge clk)
 in<=$random(seed);
 
wire [5:0] out=(in==0)?0:
               (in==1)?1:
               (in==2)?4: 
               (in==3)?9: 
               (in==4)?16: 
               (in==5)?25:  
               (in==6)?36:   
               (in==7)?49:0;  
            
initial 
begin
    $dumpfile("./ex2_3.vcd");
    $dumpvars(0,ex2_3);
end          

endmodule