ex6_5.v

来自「精通VerilogHDL：IC设计核心技术实例详解」· Verilog 代码 · 共 55 行

module ex6_5;

reg clk=0,nrst=1;
always #10 clk=~clk;
initial 
begin
   #30 nrst=0;
   #30 nrst=1;
end

reg [4:0] cntr;
always@(posedge clk or negedge nrst)
 if (~nrst)         cntr<=0;
 else if (cntr==25) cntr<=cntr;
 else               cntr<=cntr+1;
 
//source data
wire [25:0] source_data=26'b0010_1101_0111_0001_1100_0000_10;
wire #1 sd=(cntr>1)?source_data[26-cntr]:0;

//NRZI encode
reg NRZI;
always@(posedge clk or negedge nrst)
 if (~nrst)    NRZI<=0;   
 else if (~sd) NRZI<=~NRZI;
 else if ( sd) NRZI<= NRZI;
  
//NRZI decode
wire #20 prev_NRZI=NRZI;
wire NRZI_decode=(cntr>1)?(NRZI!=prev_NRZI)?0:
                          (NRZI==prev_NRZI)?1:0:0;
                   
//Compare                           
reg sd_d;
always@(posedge clk or negedge nrst)
 if (~nrst) sd_d<=0;
 else       sd_d<=sd;

always@(negedge clk)
begin
 if (sd_d!=NRZI_decode)                   
 begin        
  $display("err happen at time:%t",$time);
  $finish;
 end 
end 
                  

initial 
begin
    $dumpfile("./ex6_5.vcd");
    $dumpvars(0,ex6_5);
end          

endmodule