dff.prj

来自「精通VerilogHDL：IC设计核心技术实例详解」· PRJ 代码 · 共 48 行

#-- Synplicity, Inc.
#-- Version 7.6.1     
#-- Project file E:\project\Verilog\策肈秆氮\ex3_3\dff.prj
#-- Written on Tue Mar 22 13:53:07 2005


#add_file options
add_file -verilog "dff.v"


#implementation: "rev_1"
impl -add rev_1

#device options
set_option -technology 500K
set_option -part A500K050

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1

#map options
set_option -frequency 30.000
set_option -fanout_limit 12
set_option -maxfan_hard 0
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -report_path 4000
set_option -opcond Default
set_option -update_models_cp 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_format "edif"
project -result_file "rev_1/dff.edn"

#implementation attributes
set_option -vlog_std v2001
set_option -auto_constrain_io 0
impl -active "rev_1"