ex2_2.v

来自「精通VerilogHDL：IC设计核心技术实例详解」· Verilog 代码 · 共 26 行

module ex2_2;

//test bench
reg clk=0;
reg [7:0]in=0;
always #10 clk=~clk;
reg [1:0] sel=0;
always@(posedge clk)
 sel<=sel+1;

integer seed=4;
always@(posedge clk)
 in<=$random(seed);

//Circuit
wire [7:0] out0=(sel==0)?in:0;
wire [7:0] out1=(sel==1)?in:0;         
wire [7:0] out2=(sel==2)?in:0;
wire [7:0] out3=(sel==3)?in:0;  

initial
begin
    $dumpfile("./demux.vcd");
    $dumpvars(0,ex2_2);          
end          
endmodule