ex6_1.v

来自「精通VerilogHDL：IC设计核心技术实例详解」· Verilog 代码 · 共 30 行

module ex6_1;
//test bench
reg clk=0;
reg [3:0] a1=0,a2=0,a3=0,a4=0;
wire [3:0] y1,y2,y3,y4;
always #10 clk=~clk;

integer seed1=5,seed2=6,seed3=7,seed4=4;
always@(posedge clk)
begin 
 a1<=$random(seed1);
 a2<=$random(seed2);
 a3<=$random(seed3);
 a4<=$random(seed4);  
end 
 
comp4 comp4(//input
               a1,a2,a3,a4,
             //output y1>y2>y3>y4
               y1,y2,y3,y4
            );


initial 
begin
    $dumpfile("./ex6_1.vcd");
    $dumpvars(0,ex6_1);
end           

endmodule