comp4.v

来自「精通VerilogHDL：IC设计核心技术实例详解」· Verilog 代码 · 共 25 行

`timescale 1ns/10ps
`define raw_bits 0

module comp4(//input
               a1,a2,a3,a4,
             //output y1>y2>y3>y4
               y1,y2,y3,y4
            );
input  [`raw_bits+3:0] a1,a2,a3,a4;
output [`raw_bits+3:0] y1,y2,y3,y4;

wire [`raw_bits+3:0] max11,min11,max12,min12;
wire [`raw_bits+3:0] min13,max21,min21,min22;
wire [`raw_bits+3:0] y1,y2,y3,y4;

comp comp11(.a1(a1), .a2(a2),   .max(max11),.min(min11));
comp comp12(.a1(a3), .a2(max11),.max(max12),.min(min12));
comp comp13(.a1(a4), .a2(max12),.max(y1),   .min(min13));

comp comp21(.a1(min11),.a2(min12),.max(max21),.min(min21));
comp comp22(.a1(min13),.a2(max21),.max(y2),   .min(min22));

comp comp31(.a1(min22),.a2(min21),.max(y3), .min(y4));

endmodule