mem96x96x16.v

精通VerilogHDL：IC设计核心技术实例详解

`timescale 1ns/10ps
//-------------------------------------------------------------------------------
//-- Copyright  Roger Jane
//-- ALL RIGHTS RESERVED.
//-- This software is provided fot 8KB OTP IP verify
//-- confidential material which is the property of PTC Inc.
//--
//-- File:mem96x96x16.v 
//-- Revision:$Name: Rev0_0 $
//-- Description:
//-------------------------------------------------------------------------------
module mem96x96x16(//mcu interface
                   CS,WR,RD,DIN,
                   ROW,COL,DO,
                   
                   //driver interface
                   DISP_EN,DISP_ROW,DISP_DO);                                       
parameter

        row=96,
        col=96,        
        rowsize  =7,
        col_size =7,
        word_size = 16,
	address_size = row * col,
	display_size = row * word_size,		
	row_size = row * word_size;
	
//mcu interface   
input  CS,WR,RD;
input  [word_size-1:0] DIN; 
input  [rowsize-1:0]   ROW;
input  [col_size-1:0]  COL;
output [word_size-1:0] DO;  

//driver interface 
input  DISP_EN;
input  [rowsize-1:0]     DISP_ROW;    
output [display_size-1:0] DISP_DO;

parameter MEMSIZE=address_size-1;
reg [word_size-1:0] mem[0:MEMSIZE];
reg notifier1, notifier2, notifier3;

// Add input primitive cell for SDF annotated
wire [rowsize-1:0]  ROWx;
wire [col_size-1:0] COLx;
wire [word_size-1:0] DINx;
wire [word_size-1:0] DOUTu;
wire WRx;

buf #0.02 BUF_ROW [rowsize-1:0] (ROWx, ROW);
buf #0.02 BUF_COL [col_size-1:0] (COLx, COL);
buf #0.02 BUF_DIN [word_size-1:0] (DINx, DIN);
buf #0.02 BUF_WR  (WRx, WR);
buf #0.02 BUF_DOUTu [word_size-1:0] (DO, DOUTu);

  // Read cycle, read when address change
assign  DOUTu = (CS&RD)? mem[ROW*row_size+COLx] : 16'hz;

  // Write cycle, WEN high enable
 always @(WR) begin
   $fsdbDumpMem(mem);
   if (CS&WRx) begin
      mem[ROWx*row+COLx] <=  DINx;
   end 
 end

wire [display_size-1:0] DISP_DO;

genvar i;
generate for (i=0;i<96;i=i+1)
begin: bit
assign  DISP_DO[15+16*i:16*i]=DISP_EN? mem[DISP_ROW*col+i]:16'bz; 
end
endgenerate

specify
	specparam tds = 1.0, tdh = 0, 
		  tas = 1.0, tah = 0,
                  tw =2.0;

	// data/address setup and hold time
	$setup(DIN, posedge WR, tds, notifier1);
	$hold(negedge WR, DIN, tdh, notifier1);

	$setup(ROW, posedge WR, tas, notifier2);
	$hold(negedge WR, ROW, tah, notifier2);
	
	$setup(COL, posedge WR, tas, notifier2);
	$hold(negedge WR, COL, tah, notifier2);			
	
	//  Write enable pulsewidth 
	$width(posedge WR, tw, 0, notifier3); 

	// specify the path-delay for SDF back-annotation
	(ROW *> DO) = (3.0,3.0);
	(COL *> DO) = (3.0,3.0);

       
endspecify

always @(notifier1 or  notifier2 or notifier3) begin
	mem[ROWx*col+COLx] <= #1.01 32'hXXXX_XXXX;
end


endmodule