transcript

精通VerilogHDL：IC设计核心技术实例详解

# Reading C:/Modeltech_5.8/tcl/vsim/pref.tcl 
#  OpenFile "C:/Verilog/chap6/ch6_ex/ex6_3/mul.mpf" 
# Loading project mul
do run.do
# ** Warning: (vlib-34) Library already exists at "rtl_wrk".
# Modifying C:/Verilog/chap6/ch6_ex/ex6_3/mul.mpf
# Model Technology ModelSim SE vlog 5.8 Compiler 2003.11 Nov 11 2003
# -- Compiling module mul
# 
# Top level modules:
# 	mul
# Model Technology ModelSim SE vlog 5.8 Compiler 2003.11 Nov 11 2003
# -- Compiling module top
# 
# Top level modules:
# 	top
# vsim rtl_wrk.top 
# Loading C:\Novas\Debussy\share\PLI\modelsim_pli\WINNT/novas.dll
# Loading rtl_wrk.top
# Loading rtl_wrk.mul
# 
# Simulation Passed!
# 
# ** Note: $finish    : ./top.v(49)
#    Time: 41360 ns  Iteration: 0  Instance: /top
# 1
# Break at ./top.v line 49
# Simulation Breakpoint: 1
# Break at ./top.v line 49
# MACRO ./run.do PAUSED at line 7
pwd
# C:/Verilog/chap6/ch6_ex/ex6_3