mul.vcd

精通VerilogHDL：IC设计核心技术实例详解

$date
	Tue Feb 08 04:47:54 2005
$end
$version
	ModelSim Version 5.8
$end
$timescale
	10ps
$end
$scope module top $end
$var reg 1 ! clk $end
$var reg 1 " nrst $end
$var reg 1 # mul_en $end
$var reg 9 $ temp [8:0] $end
$var wire 1 % product [7] $end
$var wire 1 & product [6] $end
$var wire 1 ' product [5] $end
$var wire 1 ( product [4] $end
$var wire 1 ) product [3] $end
$var wire 1 * product [2] $end
$var wire 1 + product [1] $end
$var wire 1 , product [0] $end
$var wire 1 - oen $end
$var reg 4 . a_d [3:0] $end
$var reg 4 / b_d [3:0] $end
$var wire 1 0 load $end
$var wire 1 1 err_found $end
$scope module mul $end
$var wire 1 2 clk $end
$var wire 1 3 nrst $end
$var wire 1 4 a [3] $end
$var wire 1 5 a [2] $end
$var wire 1 6 a [1] $end
$var wire 1 7 a [0] $end
$var wire 1 8 b [3] $end
$var wire 1 9 b [2] $end
$var wire 1 : b [1] $end
$var wire 1 ; b [0] $end
$var wire 1 < mul_en $end
$var wire 1 - oen $end
$var reg 8 = product [7:0] $end
$var reg 2 > count [1:0] $end
$var wire 1 ? load $end
$var wire 1 @ temp [7] $end
$var wire 1 A temp [6] $end
$var wire 1 B temp [5] $end
$var wire 1 C temp [4] $end
$var wire 1 D temp [3] $end
$var wire 1 E temp [2] $end
$var wire 1 F temp [1] $end
$var wire 1 G temp [0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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$end
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