csa8_4.v

精通VerilogHDL：IC设计核心技术实例详解

`timescale 1ns/10ps
`define csawidth1 7
module csa8_4(//input
             a1,a2,a3,a4,
             a5,a6,a7,a8,
            //output
             sum);
input  [`csawidth1-4:0] a1,a2,a3,a4;
input  [`csawidth1-4:0] a5,a6,a7,a8;

output [`csawidth1:0] sum;

wire [`csawidth1:0] c_tmp1,c_tmp2,c_tmp3,c_tmp4,c_tmp5,c_tmp6;
wire [`csawidth1:0] s_tmp1,s_tmp2,s_tmp3,s_tmp4,s_tmp5,s_tmp6;

wire [`csawidth1:0] a1m={4'b0,a1};
wire [`csawidth1:0] a2m={4'b0,a2};
wire [`csawidth1:0] a3m={4'b0,a3};
wire [`csawidth1:0] a4m={4'b0,a4};

//CSA1
assign s_tmp1=a1m ^ a2m ^ a3m;
assign c_tmp1=(a1m & a2m) | (a1m & a3m) | (a2m & a3m);
wire [`csawidth1+1:0] c_tmp11={c_tmp1,1'b0};
wire [`csawidth1+1:0] s_tmp11={1'b0,s_tmp1};
wire [`csawidth1+1:0] test1= c_tmp11 + s_tmp11;

wire [`csawidth1:0] a5m={4'b0,a5};
wire [`csawidth1:0] a6m={4'b0,a6};
wire [`csawidth1:0] a7m={4'b0,a7};
wire [`csawidth1:0] a8m={4'b0,a8};

//CSA2
assign s_tmp2=a4m ^ a5m ^ a6m;
assign c_tmp2=(a4m & a5m) | (a4m & a6m) | (a5m & a6m);
wire [`csawidth1+1:0] c_tmp21={c_tmp2,1'b0};
wire [`csawidth1+1:0] s_tmp21={1'b0,s_tmp2};
wire [`csawidth1+1:0] test2= c_tmp21 + s_tmp21;      

//CSA3
assign s_tmp3=s_tmp21 ^ s_tmp11 ^ c_tmp11;
assign c_tmp3=(s_tmp21 & s_tmp11) | (s_tmp21 & c_tmp11) | (s_tmp11 & c_tmp11);
wire [`csawidth1+1:0] c_tmp31={c_tmp3,1'b0};
wire [`csawidth1+1:0] s_tmp31={1'b0,s_tmp3};
wire [`csawidth1+1:0] test3= c_tmp31 + s_tmp31;   

//CSA4
assign s_tmp4=a7m ^ a8m ^ c_tmp21[`csawidth1:0];
assign c_tmp4=(a7m & a8m) | (a7m & c_tmp21[`csawidth1:0]) | (a8m & c_tmp21[`csawidth1:0]);
wire [`csawidth1+1:0] c_tmp41={c_tmp4,1'b0};
wire [`csawidth1+1:0] s_tmp41={1'b0,s_tmp4};
wire [`csawidth1+1:0] test4= c_tmp41 + s_tmp41;      

//CSA5
assign s_tmp5=s_tmp41 ^ c_tmp31 ^ s_tmp31;
assign c_tmp5=(s_tmp41 & c_tmp31) | (s_tmp41 & s_tmp31) | (c_tmp31 & s_tmp31);
wire [`csawidth1+1:0] c_tmp51={c_tmp5,1'b0};
wire [`csawidth1+1:0] s_tmp51={1'b0,s_tmp5};

//CSA6
assign s_tmp6=c_tmp41 ^ c_tmp51 ^ s_tmp51;
assign c_tmp6=(c_tmp41 & c_tmp51) | (c_tmp41 & s_tmp51) | (c_tmp51 & s_tmp51);
wire [`csawidth1+1:0] c_tmp61={c_tmp6,1'b0};
wire [`csawidth1+1:0] s_tmp61={1'b0,s_tmp6};

wire [`csawidth1:0] sum=c_tmp61+s_tmp61;

endmodule