ex2_6.v

来自「精通VerilogHDL：IC设计核心技术实例详解」· Verilog 代码 · 共 29 行

module ex2_6;
//test bench
reg clk=0,nrst=1,sel=0;
reg [7:0] din=0,dout;
always #10 clk=~clk;
initial begin
 #50 nrst=0;
 #70 nrst=1;
 #80 sel=1;
 #15 sel=0;
end

integer seed=4;
always@(posedge clk)
 din<=#1 $random(seed);
 
wire [7:0] temp={dout[1:0],dout[7:2]};
always @(posedge clk or negedge nrst)
 if (~nrst)       dout<=0;
 else if (sel==1) dout<=din;
 else             dout<=temp;
 
initial 
begin
    $dumpfile("./ex2_6.vcd");
    $dumpvars(0,ex2_6);
end           

endmodule